input delay for an input path

ro9ty said:

By default all input/output are unconstrained. Execute any timing command from/to the ports and they will state it is unconstrained.
You can assume it to be your first step before synthesis, although many times if the design is not so timing critical (expected) the you can go ahead with the synthesis without it and worry about closing the timing in STA phase later.
It is just like - You cannot start an auction unless you have mentioned the base price. You constrain it loosely and then as your design progresses and you observe violations (if any) you constrain it tighter.

GLS cannot help unless you constrain it too.

Ro9ty

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sun_ray said:

Let the question be framed gain since we did not still get the answer of our question.

Question: Suppose I have a design to synthesize. I constrained all the path. But I missed by mistake to constraint only one path which was an path from an input to a flipflop as depicted in the attached diagram in post number 1. But that path was a time critical path. Afterwards the synthesis was done. Now the synthesis timing report showed all paths met timing. So we concluded timing was met. But we did not know that there was one path which was not constraint and it was the timing critical path. Our question is now how to take care of such a situation so that we do not conclude that timing has met while we missed to constraint some paths by mistake.

Please let us know if the question is not still clear.

Regards

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sun_ray said:

Let the question be framed gain since we did not still get the answer of our question.

Question: Suppose I have a design to synthesize. I constrained all the path. But I missed by mistake to constraint only one path which was an path from an input to a flipflop as depicted in the attached diagram in post number 1. But that path was a time critical path. Afterwards the synthesis was done. Now the synthesis timing report showed all paths met timing. So we concluded timing was met. But we did not know that there was one path which was not constraint and it was the timing critical path. Our question is now how to take care of such a situation so that we do not conclude that timing has met while we missed to constraint some paths by mistake.

Please let us know if the question is not still clear.

Regards

Click to expand...

layowblue said:

By saying "Now the synthesis timing report showed all paths met timing", you are conflicting yourself's statement that "I missed by mistake to constraint only one path which was an path from an input to a flipflop".
Logically, we can draw the conclusion that your "synthesis timing report" is not exhaustive or complete enough for sign-off.
A well-architected synthesis flow should have timing reports(or warnings) on paths that are "UNCONSTRAINED".
If you don't have a methodology for synthesis flow, you need to create your own script/tcl to tell the synthesis tool to generate timing reports for input/output related path.
When you get the reports, search for "unconstrained" and you'll get it quickly.

In addition, SDC is one of the most important deliverables designers own. Missing an input constraint is a huge mistake. You should take this as a serious lesson.

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sun_ray said:

Do you want to mean that the report_timing also reports the unconstrained paths along with constraint paths?

Regards

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