sammm
Newbie level 5
- Joined
- Jan 8, 2005
- Messages
- 9
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Activity points
- 94
verilog st0
Hi,
I am new for the area of HDL programing, what I am trying to do is to create a finite state machine that only have three stages :
ST0 : initial state
ST1 : stay in this stage for 32 times
ST3 : finish then return to ST0
I know that its very simple but for some reason, I can't do it right, here is the code that I wrote :
What I want to do after getting this simple model work is to add some extra code to the state ST1, I don't want to implement a counter, so if there is any other style to do it please advice...
Thank you
Hi,
I am new for the area of HDL programing, what I am trying to do is to create a finite state machine that only have three stages :
ST0 : initial state
ST1 : stay in this stage for 32 times
ST3 : finish then return to ST0
I know that its very simple but for some reason, I can't do it right, here is the code that I wrote :
Code:
module fsm (count, clk, reset, ready);
output [4:0] count;
output ready;
input clk;
input reset;
reg ready;
reg [4:0] count;
parameter ST0=0, ST1=1, ST2=2;
reg [1:0] CurrentState, NextState;
always @(CurrentState)
begin
case(CurrentState)
ST0: begin
count= 0;
ready= 0;
NextState= ST1;
end
ST1: begin
if(count < 32)
begin
count = count + 1;
NextState = ST1;
end
else
NextState = ST2;
end
ST2: begin
ready = 1;
NextState = ST0;
end
default:begin
ready = 0;
NextState = ST0;
end
endcase
end
always @(posedge clk or posedge reset)
begin
if(reset)
CurrentState= ST0;
else
CurrentState=NextState;
end
endmodule
What I want to do after getting this simple model work is to add some extra code to the state ST1, I don't want to implement a counter, so if there is any other style to do it please advice...
Thank you