Why do we need zero-delay netlist simulation?

We can make use of the logic equivalence tools like Cadence Conformal LEC or Synopsys Formality to verify the logical equivalence between the netlist and RTL.

Above this, I could not understand why do we need to do zero-delay netlist simulation. Can we skip zero-delay netlist simulation if the netlist and RTL are proved to be logically equivalent using LEC or Formality ?

Heh, very good question, I sometimes wonder myself this question. I think zero-delay netlist simulation is needed just for reassurance, because formal-verification tools not always behave correctly(I often face with mapping problems, and false nonequivalences), as well as synthesis tools. Also, there are nuances of simulation of gate-level netlist occurs sometimes. And in general, good IC developer must be paranoid, and verify design at all stages using all available means, because mask patterns re-order costs a lot of money))

Hi ivb1991,

I am sure it is not just about reassurance. Some experienced engineers should be able to tell us.
Two reasons I could think of are Block-boxes and resets.

1. Generally during LEC, analog blocks such as PLL, Transceivers and memories will be block-boxed. But during simulation we will have an equivalent model for those block-boxes.
2. Reset ports would be set to a constant value during LEC.

I would like to hear from senior boarders more.

The point 1 could be a reason.
For the point 2, I never set the RESET ports during LEC.

In our design center, we never simulate zero-delay netlist simulation, but only timing-nelist simulation, to confort the STA constraints do not maske any real paths.

Hi rca,

Even point 1 may not be the reason, as we use the same models during RTL simulation too.
I am still breaking my head to find out why we do !

would be great if someone comes up with the real reason.

So it seems that each company have its own design flow, which may not include zero-delay netlist simulation.
In our current project(in which I participate) we run regressions on zero-delay pre-layout netlist because running regression for post-layout+SDF is too long(several weeks, depends on servers performance).
When pre-layout netlist is verified by regression, we verify post-layout by LEC with pre-layout. The simulation of final post-layout ideally runs only once just before the sign-off.

So ivb1991, you need to check very carefully the STA constraints to have good timing reports and to not miss anything.
I don't really see the goal of the zero-delay netlist, but that's your choice .
I suppose if you need to reach a power target, you run some timing netlist simulation?

rca said:

So ivb1991, you need to check very carefully the STA constraints to have good timing reports and to not miss anything.
I don't really see the goal of the zero-delay netlist, but that's your choice .
I suppose if you need to reach a power target, you run some timing netlist simulation?

Click to expand...

STA is not my job, but as I know constraints could be verified automatically by tools like Encounter CCD.
Estimation of power consumption... it doesn't require running full regression simulation of post-layout+SDF.

As per your customer's deman you may or may not do zero-delay GLS. However, GLS with annotated SDF is often done but i will stick to your query.
In order to prove a design equivalent we have to often add some constraints or layoff some blocks. Ex. If you have DSP blocks you would prefer to black-box them and then do a formal check separately with DSP as root. In many of these cases and some more, some points are not covered, they become unmapped points which the designer reviews. If he feels that they can be wavered as the design team expects an unmapped point there since it is unreachable (connected to Black box etc..) but if not so, and LEC is clean with some fishy unmapped pointss then you would like to double check it with zero-delay GLS.

- - - Updated - - -

You may find this link useful :-
http://whatisverification.blogspot.in/2011/06/gate-level-simulations-necessary-evil.html

I don't recall anyone I know ever running at zero-delay gate-level sim.

Of course, equivalence checking tools haven't always been around and you might want to run a sim on a netlist that has timing violations that haven't yet been fixed. By running with zero-delay, you may be able to avoid those violations from breaking the sim. (Although you may also cause other problems).

You guys are talking two different things.

LEC conformal is equivalency check where you try to find out that tool has not done any extra ordinary job during optimization , this is just to check the logic equivalency.

zero delay gate level simulation , this is too check if your simulation is working correctly with netlist or not , ideally with no SDF there should not be any issue, but you will face 'X' propagation because of gate delay and sync cells.

For sync cells , you need to turn off timing checks , that you can do without SDF.

So once you have SDF, then it will be very difficult to identify the issue , it may be because of sync cells or because of timing violations or because of flow setup.
It is always advisable to run zero delay simulation, it will save a lot of debugging time when you run simulation with SDF.


one of person has asked the same question ..

Yes Rahul, i completely agree it is advisable to do the zero-delay GLS but since the advancement of LEC tools we don't do it. You can also check for X propagation through gates using LEC tool.
In general if you have to do a clean synthesis with LEC absolutely clean and hand it over to a client then you might do GLS with 1 delay to prove your point but otherwise we generally avoid it if LEC comes clean.

If you are using formality instead of conformal, you can even know details of the optimization done by Synthesis tool.

Ro9ty

I have given a thought about this again. Sometimes inaccurate specification of `timescale in a Verilog RTL may cause test failure. I think zero delay simulation should help us find out and overcome such kind of RTL issues.