ivlsi
Advanced Member level 3
Hi All,
What's the methodology to make a FIRST synthesis without WLM (after this first run, the netlist will be passed to P&R for creation a Custom WLM)?
Should the clock frequency and in/out inputs be over-constrained? How much?
Thank you!
What's the methodology to make a FIRST synthesis without WLM (after this first run, the netlist will be passed to P&R for creation a Custom WLM)?
Should the clock frequency and in/out inputs be over-constrained? How much?
Thank you!