VHDL enumerated type _ basic question

This is a very basic question in VHDL. I am askign this after unable to find a clear answer in various internet pages.

In VHDL, we use the ENUMERATION type. Normally a type is defined even for a signal, however, here for enumerated type it just goes like



so the object type like std_logic, or bit or similar thing is not specified to this enemurated type COLOR. Can I use one of its component lets say Blue for a bit, green for a signed bit vector, etc?

Can somone explain the logic behing this?

Thanks in advance.

graphene said:

...
so the object type like std_logic, or bit or similar thing is not specified to this enemurated type COLOR. Can I use one of its component lets say Blue for a bit, green for a signed bit vector, etc?

Click to expand...

std_logic is defined in the following manner:

Hence, std_logic is a subtype of the enumerated type std_ulogic.

graphene said:

Can somone explain the logic behing this?

Click to expand...

VHDL is a strongly typed language. You may only use two types together if they are the same or one is a subtype of the other (like std_logic and std_ulogic). Hence, you may not assign a value of COLOR to nex and you may not assign a value of std_logic to nex.

What you are really struggling with is, "How does the synthesis tool assign bit values to my state vector?" This is a process that is independent of the language. To get something particular you will have to learn about the statemachine attributes your synthesis supports - unfortunately the synthesis vendors have ignored IEEE attempts to standardize this.

If you are employed by a profitable company, you might want to consider taking a VHDL class (such as one from SynthWorks - my company) or if not, invest in a good book.

Jim

In many cases, an enumeration type is similar to an integer range, e.g. the states of a finite state machine. As explained, it's not possible to use it in a different, incompatible enumeration. And it would neither make sense, I think.

thank you Synthworks.

I got your points.

Let me think this as an language independant attribute though no textbook makes sense with this regard.


thankyou FvM... I actually do not want to mix the signals aber just to know as in what is happening. thanks for your time...