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'Low Power VLSI' : Project guidance help needed.

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gstekboy

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I'm Studying M.tech VLSI , as a part of my course I selected 'Low Power VLSI' as my project domain.
My idea is to work on 'Low Power Multiplier' to minimize it's power , delay and increase the speed of multiplier.
I don't know whether the multiplier domain is saturated or not . Is there any good area other than multiplier in Low Power VLSI ?
 

If you are working at the transistor-level circuitry for the digital multiplier, then it's not saturated at all..

If you opt for designing a multiplier based on Current-Mode Multi-Valued Logic (MVL), believe me, it has tremendous scope for research, which you can continue for PhD also. MVL uses more than two logic levels to define a signal (unlike binary logic)..

Furthermore, you can try some additional feature for multiplier, like Reversible Logic, Vedic Multiplier, Signed Multiplier, etc..

But you'll have to work hard..

All The Very Best...
 
pavan garate said:
If you are working at the transistor-level circuitry for the digital multiplier, then it's not saturated at all..

If you opt for designing a multiplier based on Current-Mode Multi-Valued Logic (MVL), believe me, it has tremendous scope for research, which you can continue for PhD also. MVL uses more than two logic levels to define a signal (unlike binary logic)..

Furthermore, you can try some additional feature for multiplier, like Reversible Logic, Vedic Multiplier, Signed Multiplier, etc..

But you'll have to work hard..

All The Very Best...
Click to expand...



Thanks for your valuable suggestion.
Going to concentrate more about vedic multiplier.
 
Last edited:

gstekboy said:
Going to concentrate more about vedic multiplier.
Click to expand...

You can implement a Vedic multiplier using-
1) Hardware Description Language (HDL) such as VHDL or Verilog
OR
2) Transistor-level circuitry

I'll suggest you the 2nd option. But make any decision after discussing with your guide & also considering the tools available at your institute.

After taking this decision, you may proceed by reading as much research papers as you can.
 
pavan garate said:
You can implement a Vedic multiplier using-
1) Hardware Description Language (HDL) such as VHDL or Verilog
OR
2) Transistor-level circuitry

I'll suggest you the 2nd option. But make any decision after discussing with your guide & also considering the tools available at your institute.

After taking this decision, you may proceed by reading as much research papers as you can.
Click to expand...
As there is no journal paper available in ieee it is difficult to find a base paper for vedic multiplication.
 

Thanks for the multiplier pipelining technique.
 

I think you should go for GDI technique. It stands for Gate Diffusion Input Techniques. It uses almost 50% less transistors than other techniques. It consume low power and speed is little higher than other techniques.Many VLSI students are working on GDI and designing various blocks as it uses very less area so for compact design it is preferred.I am sending you link of GDI technique.

**broken link removed**

Even i had proposed one paper on it.the link is below.

**broken link removed**
 
Thanks for the GDI technique.
 

Although Vedic is not focussed on low power designing, it uses less circuitry as compared to conventional multiplier, which may reduce the power.

Pipelining is surely a technique focussed on power consumption if you are ready to sacrifice the area...
 
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