Hierarchical error in block

arishsu · Mar 9, 2014

Hi
I am getting an error when synthesized the code

WARNING:Xst:1290 - Hierarchical block <TIM1> is unconnected in block <digital_lock_top>.
It will be removed from the design.

The top block is

Code Verilog - [expand]
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module digital_lock_top(key,unlock,alarm,display_code,clk_50Mhz,lock_reset,door_sensor);
input[0:9]key;
input clk_50Mhz,door_sensor,lock_reset;
output alarm,unlock;
output [6:0]display_code;
wire key_code,key_dep,code_sw,any_sw,timeout,select_timeout,en_tim1;
wire [1:0] select;
 
clock_divider CLK_DIV(clk_50Mhz,clk);
key_pad_ckt KEY_PAD(key,select,key_code,key_dep);
lock_FSM_controller FSM(code_sw,any_sw,lock_reset,clk,timeout,select_timeout,unlock,alarm,en_tim1,select);
fall_edge_detector FALL_ED(key_code,clk,key_dep,code_sw,any_sw);
timer1 TIM1(clk,en_tim1,door_sensor,timeout);
timer2 TIM2(clk,code_sw,select_timeout,select);
display_decoder DISPLAY(unlock,alarm,display_code);
 
endmodule

And code for timer1 is

Code Verilog - [expand]
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module timer1(clk,en_tim1,door_sensor,timeout);
input clk,en_tim1,door_sensor;
output timeout;
reg timeout;
reg [14:0]count;
initial begin
    timeout=0;
end
always@(posedge en_tim1)
 begin
    count=15'b000000000000111;//assuming clk=1KHz, count=32.7 sec
 end
always@(posedge clk)
begin
    if(!en_tim1 || !door_sensor)
    begin
        timeout=0;
    end
    else if(en_tim1 && door_sensor && count>0)
    begin
        count=count-1;
        timeout=(count==0)?1:0;
    end
    else if (!en_tim1 && door_sensor)
        begin
            timeout=0;
        end
end     
endmodule

ads-ee · Mar 10, 2014

There is nothing wrong with your TIM1 instance, besides the lack of white space to improve readability and the lack of named port mapping.

Your problem is probably in the lock_FSM_controller, but since you didn't include the code can't help you further.

Check your reports you probably have the timeout signal connected to the wrong port (which is why you should always use named port mapping) on the FSM and/or it's not used in that module.

regards

arishsu · Mar 10, 2014

Hi ads-ee
Named port mapping is a bit confusing to me. I don't use that much.

The code for lock_FSM_controller is

Code:

module lock_FSM_controller(code_sw,any_sw,lock_reset,clk,timeout,select_timeout,unlock,alarm,en_tim1,select);
input code_sw,any_sw,lock_reset,clk,timeout,select_timeout;
output reg unlock,alarm,en_tim1;
output reg [1:0]select;
parameter s0=3'b000,
			 s1=3'b001,
			 s2=3'b010,
			 s3=3'b011,
			 unlock_state=3'b100,
			 wrong=3'b101;
reg [2:0] lock_state;
initial lock_state=s0;
always@(negedge clk or posedge lock_reset)
 begin
	if(lock_reset)
		lock_state<=s0;
	else 
	 case(lock_state)
		s0: if(code_sw && any_sw) lock_state<=s1;
			 else if (any_sw) lock_state<=wrong;
		s1: if(select_timeout) lock_state<=s0;
			 else if(code_sw && any_sw) lock_state<=s2;
			 else if (any_sw) lock_state<=wrong;
		s2: if(select_timeout) lock_state<=s0;
			 else if(code_sw && any_sw) lock_state<=s3;
			 else if (any_sw) lock_state<=wrong;
		s3: if(select_timeout) lock_state<=s0;
			 else if(code_sw && any_sw) lock_state<=unlock_state;
			 else if (any_sw) lock_state<=wrong;
		unlock_state: if(timeout) lock_state<=s0;
						  else lock_state<=unlock_state;
		wrong: if(lock_reset) lock_state<=s0;
				 else lock_state<=wrong;
	 endcase
 end
always@(lock_state)
 begin
	case(lock_state)
		s0: begin
				unlock=0;
				alarm=0;
				en_tim1=0;
				select=2'b00;
			 end
		s1: begin
				unlock=0;
				alarm=0;
				en_tim1=0;
				select=2'b01;
			 end
		s2: begin
				unlock=0;
				alarm=0;
				en_tim1=0;
				select=2'b10;
			 end
		s3: begin
				unlock=0;
				alarm=0;
				en_tim1=0;
				select=2'b11;
			 end
		unlock_state: begin
							unlock=1;
							alarm=0;
							en_tim1=1;
							select=2'b00;
						  end
		wrong: begin
					unlock=0;
					alarm=1;
					en_tim1=0;
					select=2'b00;	
				 end
	endcase
 end
endmodule

Regards

nikhilna007 · Mar 10, 2014

in the instantiation
timer1 TIM1(clk,en_tim1,door_sensor,timeout);

you should declare clk as an input or reg
you have not declared

you have only declared clk_50mhz.

its confusing me

ads-ee · Mar 10, 2014

Named port mapping is a bit confusing to me. I don't use that much.

Confusing? you have to be kidding.

How is this confusing?

Code Verilog - [expand]
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timer1  TIM1 (
  .clk         (clk),
  .en_tim1     (en_tim1),
  .door_sensor (door_sensor),
  .timeout     (timeout)
);

v.s.

Code Verilog - [expand]
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timer1 TIM1(clk,en_tim1,door_sensor,timeout);

With the first you can write ports in any order as each port .port_name is explicitly connected to a wire (wire_name).

Can't quickly see anything wrong with the use of timeout in the FSM, seems like it should be connected. You should carefully look over the .syr file generated by XST to see if something is getting removed that shouldn't be.

Why are you using negedge clk in the FSM? You're using the posedge clk in other modules and some of those signals like timeout go to the FSM.

regards

arishsu · Mar 11, 2014

nikhilna007 said:
in the instantiation
timer1 TIM1(clk,en_tim1,door_sensor,timeout);

you should declare clk as an input or reg
you have not declared

you have only declared clk_50mhz.

its confusing me

Yes I missed that one. Initially I designed with a single clock and then I added clk_50Mhz so that I can use the on-board clock. I corrected it but still the problem is there. Shows the same warning and timer1 block is not shown in schematic.

- - - Updated - - -

ads-ee said:
Confusing? you have to be kidding.

Can't quickly see anything wrong with the use of timeout in the FSM, seems like it should be connected. You should carefully look over the .syr file generated by XST to see if something is getting removed that shouldn't be.

Why are you using negedge clk in the FSM? You're using the posedge clk in other modules and some of those signals like timeout go to the FSM.

I used negedge so that it doesn't take an extra clock pulse to react like when pressing the key. So I gave all other blocks posedge and FSM a negedge. But I think if I'm using high frequency clk it won't make any difference. But I'm worried about switch debounce and so I am intending to give a low frequency clk. Since timer1 block is not showing, I can't run it on hardware so that I can check it.

ads-ee · Mar 11, 2014

arishsu said:
I used negedge so that it doesn't take an extra clock pulse to react like when pressing the key. So I gave all other blocks posedge and FSM a negedge. But I think if I'm using high frequency clk it won't make any difference. But I'm worried about switch debounce and so I am intending to give a low frequency clk. Since timer1 block is not showing, I can't run it on hardware so that I can check it.

No, don't run an external signal into an FSM unless it is ALREADY debounced and synchronized to the FSM clock domain. You don't use an FSM to debounce signals you should add a synchronizer and debounce circuit to the signal that you are going to send to the FSM.

Do a search for debounce circuits.

- - - Updated - - -

nikhilna007 said:
in the instantiation
timer1 TIM1(clk,en_tim1,door_sensor,timeout);

you should declare clk as an input or reg
you have not declared

you have only declared clk_50mhz.

its confusing me

Good catch didn't even notice that. This is another example of why code formatting is extremely important to code correctness and maintainability. The OPs code is very hard to read without reformatting (which I didn't do).

nikhilna007 · Mar 14, 2014

please upload the new code with the changes

arishsu · Apr 8, 2014

I solved that problem and the problem was with timer 1 module. I used the register count in two different always blocks. when I corrected that, it worked. This my full code. But still it has problem with switch bounce.

Code:

module digital_lock_top(key,unlock,alarm,display_code,clk_50Mhz,lock_reset,door_sensor);
input[0:9]key;
input clk_50Mhz,door_sensor,lock_reset;
output alarm,unlock;
output [6:0]display_code;
wire key_code,key_dep,code_sw,any_sw,timeout,select_timeout,en_tim1,clk;
wire [1:0] select;

clock_divider CLK_DIV(clk_50Mhz,clk);
key_pad_ckt KEY_PAD(key,select,key_code,key_dep);
lock_FSM_controller FSM(code_sw,any_sw,lock_reset,clk,timeout,select_timeout,unlock,alarm,en_tim1,select);
fall_edge_detector FALL_ED(key_code,clk,key_dep,code_sw,any_sw);
timer1 TIM1(clk,en_tim1,door_sensor,timeout,lock_reset);
timer2 TIM2(clk,code_sw,select_timeout,select);
display_decoder DISPLAY(unlock,alarm,display_code);

endmodule
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
module clock_divider(clk_50Mhz,clk);
input clk_50Mhz;//input from spartan 3E- 50MHz clock
output clk;//Output clk required- 1Khz
reg clk ;

reg [15:0] m;//16 bit register for the divider- needed a count 50,000
initial m = 0;//initial count = 0

always @ (posedge clk_50Mhz)
begin
 if (m<50)
  m <= m + 1;
 else   
  m <= 0;
end

always @ (m) begin//for every change in m, this loop is entered
 if (m<25)//50% duty cycle- clk=1 for m=25000 & clk=0 for the next half
  clk <= 1;
 else
  clk <= 0;
end
endmodule
///////////////////////////////////////////////////////////////////////////
module key_pad_ckt(key,select,key_code,key_dep);
input [0:9] key;
input [1:0] select;
output key_code,key_dep;
assign key_dep=&key;
mux M1(key[7],key[0],key[6],key[9],key_code,select);
endmodule

module mux(i0,i1,i2,i3,out,s);
input i0,i1,i2,i3;
input[1:0]s;
output out;
assign out=(s[1]==0)?((s[0]==0)?i0:i1):((s[0]==0)?i2:i3);
endmodule
//////////////////////////////////////////////////////////////////////////////
module lock_FSM_controller(code_sw,any_sw,lock_reset,clk,timeout,select_timeout,unlock,alarm,en_tim1,select);
input code_sw,any_sw,lock_reset,clk,timeout,select_timeout;
output reg unlock,alarm,en_tim1;
output reg [1:0]select;
parameter s0=3'b000,
			 s1=3'b001,
			 s2=3'b010,
			 s3=3'b011,
			 unlock_state=3'b100,
			 wrong=3'b101;
reg [2:0] lock_state;
initial lock_state=s0;
always@(negedge clk or posedge lock_reset)
 begin
	if(lock_reset)
		lock_state<=s0;
	else 
	 case(lock_state)
		s0: if(code_sw && any_sw) lock_state<=s1;
			 else if (any_sw) lock_state<=wrong;
		s1: if(select_timeout) lock_state<=s0;
			 else if(code_sw && any_sw) lock_state<=s2;
			 else if (any_sw) lock_state<=wrong;
		s2: if(select_timeout) lock_state<=s0;
			 else if(code_sw && any_sw) lock_state<=s3;
			 else if (any_sw) lock_state<=wrong;
		s3: if(select_timeout) lock_state<=s0;
			 else if(code_sw && any_sw) lock_state<=unlock_state;
			 else if (any_sw) lock_state<=wrong;
		unlock_state: if(timeout) lock_state<=s0;
						  else lock_state<=unlock_state;
		wrong: if(lock_reset) lock_state<=s0;
				 else lock_state<=wrong;
	 endcase
 end
always@(lock_state)
 begin
	case(lock_state)
		s0: begin
				unlock=0;
				alarm=0;
				en_tim1=0;
				select=2'b00;
			 end
		s1: begin
				unlock=0;
				alarm=0;
				en_tim1=0;
				select=2'b01;
			 end
		s2: begin
				unlock=0;
				alarm=0;
				en_tim1=0;
				select=2'b10;
			 end
		s3: begin
				unlock=0;
				alarm=0;
				en_tim1=0;
				select=2'b11;
			 end
		unlock_state: begin
							unlock=1;
							alarm=0;
							en_tim1=1;
							select=2'b00;
						  end
		wrong: begin
					unlock=0;
					alarm=1;
					en_tim1=0;
					select=2'b00;	
				 end
	endcase
 end
endmodule
////////////////////////////////////////////////////////////////////
module fall_edge_detector(key_code,clk,key_dep,code_sw,any_sw);
input key_code,clk,key_dep;
output code_sw,any_sw;
FED F1(key_code,clk,code_sw),
	 F2(key_dep,clk,any_sw);
endmodule

module FED(in,clk,out);
input in,clk;
output out;
wire q0,q1;
D_FF D1(in,clk,q0),
	  D2(q0,clk,q1);
assign out=(q0 && !q1);
endmodule

module D_FF(d,clk,q);
input d,clk;
output reg q;
always@(negedge clk)
 begin
  q<=d;
 end
endmodule
///////////////////////////////////////////////////////////////////////
//**********************TIM1*****************************************
module timer1(clk,en_tim1,door_sensor,timeout,lock_reset);
input clk,en_tim1,door_sensor,lock_reset;
output timeout;
reg timeout;
reg [14:0]count;
initial begin
	timeout=0;
	count=15'b000000000000111;//assuming clk=1KHz, count=32.7 sec
end
/*always@(posedge en_tim1)
 begin
	count=15'b000000000000111;//assuming clk=1KHz, count=32.7 sec
 end*/
always@(posedge clk)
begin
	if(!en_tim1 || !door_sensor)
	begin
		timeout=0;
	end
	else if(en_tim1 && door_sensor)
	begin
		count=count-1;
		timeout=(count==0)?1:0;
	   //timeout=~|count;
	end
	if(timeout || !door_sensor || lock_reset)
		begin
		count=15'b000000000000111;
		end
	/*else if (!en_tim1 && !door_sensor)
		begin
			timeout=0;
		end*/
end		
endmodule
/////////////////////////////////////////////////////////////////////////
module timer2(clk,code_sw,select_timeout,select);
input clk,code_sw;
input [1:0]select;
output reg select_timeout;
reg [12:0]count;
initial begin
select_timeout=0;
//count=13'bx;
end
always@(posedge clk)
begin
	if(code_sw && select<3)
	begin
		count=13'b0000000000111;
	end
	else if(code_sw && select==3)
	begin
		count=13'b0;
	end
	else if(count>0)
	begin
		count=count-1;
		select_timeout=(count==0)?1:1'b0;
	end
	else select_timeout=1'b0;
	//else if(unlock)
	//	select_timeout=1'b0;
end
endmodule
///////////////////////////////////////////////////////////////////////
module display_decoder(unlock,alarm,display_code);
input unlock,alarm;
output reg[6:0]display_code;
initial display_code=7'b0;
always@(alarm or unlock)
 begin
	if(!unlock && !alarm)
		display_code=7'b0001110;
	else if(unlock && !alarm)
		display_code=7'b0111110;
	else if(!unlock && alarm)
		display_code=7'b1110111;
	else display_code=7'b0;
 end
endmodule
/////////////////////////////////////////////////////////////////////////

ads-ee · Apr 8, 2014

I suggested you do a search for debounce circuits in post #7.

https://www.lmgtfy.com/?q=verilog+debounce+code

The first hit has a circuit, which looks very similar to my parameterized common library component that I developed.

Welcome to EDAboard.com

Hierarchical error in block

arishsu

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arishsu

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nikhilna007

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