brasilino
Newbie level 4
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Hi,
I'm not a Verilog guru but have some experience. My question is about how a always block is synthetized in hardware, not its behaviour.
let's suppose I've got an always block as:
Since I'm using a blocking assigment and y is a 1-bit reg, it should be inferred as a FF, so it should need some pulse signal to latch the previous bitwise operation result.
My question is: once synthetized in a FPGA, this circuit seems to need a sequence of 3 clock-like pulse signal, one for each assignment. Am I right ?
Thanks!
regards
Brasilino
I'm not a Verilog guru but have some experience. My question is about how a always block is synthetized in hardware, not its behaviour.
let's suppose I've got an always block as:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 input wire a, b, c; output reg y; always @(*) begin y = a; y = y & b; y = y & c; end
Since I'm using a blocking assigment and y is a 1-bit reg, it should be inferred as a FF, so it should need some pulse signal to latch the previous bitwise operation result.
My question is: once synthetized in a FPGA, this circuit seems to need a sequence of 3 clock-like pulse signal, one for each assignment. Am I right ?
Thanks!
regards
Brasilino
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