[SOLVED] Difference between physically exclusive and logically exclusive clock groups ?

Design compiler and Primetime provides an option to set two clock groups as logically exclusive or physically exclusive as follows.

set_clock_groups -physically_exclusive/-logically_exclusive

What are the scenarios under which we should set two clock groups as physically exclusive or logically exclusive?

Hi,


Logically Exclusive:
Consider a scenario where your block has two clocks coming from top level, say CLKA & CLKB as seen in the figure 1, and there are timing paths from CLKA -> CLKB and/or CLK -> CLKB. If you are sure for some reason, you don't want to time(don't worry about timing) these paths then you can use the logically exclusive switch with the set_clock_groups.

Lets consider a second scenario as seen in figure 2:
CLK1 and CLK2 are mux-ed and the output of the mux driving few flops. In this case, both the clocks will be reaching all the destination flops through the clock-mux. The timing-tool will try to check timing between CLK1 and CLK2 for the same set of flops. In this case both the clocks can never be present, only one clock will be reaching the flop clock pins through the mux based on the select signal Sel. In this case if you use logically exclusive switch then if there are any other timing paths from CLK1 and CLK2, even those wont be considered for timing, so in this case physically_exclusive is used.

Please correct me if my understanding is incorrect.

Nice to see another Vasanth in this blog !!
Hi from where did you get the attached picture (physically_exclusive.png)? I just feel your explanation is not right.
Maybe if you give the source I can dig further.

From what I have read in the internet,

Logically exclusive means - Both the clocks(or clock groups) can exist (can be active) simultaneously in the design and the clocks have SI impact on each other’s clock domain

Physically exclusive means - Both the clocks(or clock groups) cannot exist (cannot be active) simultaneously in the design and the clocks have no SI impact on each other’s clock domain.

Yes, looks like my explanation is not appropriate.
It was my understanding which I noted down in my previous response.

Your explanation from what you have found on internet is correct from what I understand now.
Lets see if someone gives us a better understanding.

Thanks

The differences between -async , physically_exclusive , logically_exclusive for command set_clock_groups during crosstalk analysis are the following:



physically_exclusive:

Means Timing paths between these clock domains are false, but only one clock can exist in the design at the same time. ETS/Tempus will filter out the SI interactions of nets/paths between these groups.
To phrase it differently, if the clocks are exclusive, then there should be no SI victim/aggressor interaction at all between nets clocked by physically excluded clocks.

asynchronous

If two clocks are asynchronous, it means that they don't have any phase relationship among them at all. So instead of using definite timing windows based on arrival times/skew etc, the tool will use infinite timing windows when calculating aggressors and victims, therefore you will see maximum SI impact.

logically_exclusive

Logically exclusive means the timing paths between these clock domains are false, but both clocks can exist in the design at the same time, so SI interactions between paths in these domains should still be considered. However crosstalk analysis will be done with regular timing windows based on arrival times/skew etc.

Hi Kirtesh,

Could you list down two or three practical examples in a chip or ip or any design for physically_exclusive clock groups ?
Would be great and helpful if you can list them with some diagram.

Thanks

Hi Vasanth , hope this will help you , please find attached file unzip it and enjoy..

Kritesh,

This is a solvnet material right ? I have gone through that already. Anyway thanks for sharing !
What I have noticed is that they are declaring additional generated clocks at the input of the mux and they are declaring them as physically exclusive so that clock upstream of the mux will become physically exclusive, whereas the clocks downstream the mux can still be declared as logically exclusive.

Is it that only at the input of the mux we can declare two clock groups as physically exclusive ? or is there any other practical scenarios are there ?

One example which I can think of physically exclusive clocks is an ATE clock (Automatic test equipment) and a design clock

Hi sharath,

Is it because the ATE clock and the design clock share the same clock port at the chip level I/O. Please correct me if I am wrong.

What is generally the frequency of ATE clock ? Do we need to do timing closure of the design with respect to the ATE clock as well ?

Thanks

The ATE clock and the design clock will share the same clock port. That is why at any time only one of them will reach the design.
We need not close the timing with respect to teh ATE clock frequency. Usually their frequency will be lower compared to the design clock frequency.

Assume that from your chip two data buses are going to UART module or USART. One of them will transmit, other will recieve. One is triggered by Tclk other by Rclk (same frequency say) Now, they can co-exist but if our design is not duplex (i.e only one of them can exist at a time) then we have to make sure that STA tool does not check for any violation between these two clocks. thats when we set logically_exclusive.
Now, say it is duplex... the two clocks can co-exist and work on different paths.. so they might not be having any timing paths in common but during SI analysis it has to be taken into consideration since both of them could be switching at same time (same 0r opposite direction) and thus make an SI impact. So, it cannot be set as physically exclusive.
Physically exclusive would be something like two clocks going into a mux and coming out. According to SEL only one of them can exist and thus SI computation on both would be overtly pessimistic.
Not just mux, there could be many examples.. There could be clocks coming out of dividers, mux, out of special combo cells like OA (Or anded) etc.. It could also be clocks coming from port and going through a bypass logic.