[SOLVED] Set library attributes for Cadence RTL compiler Synthesis

I would like to write script for Cadence RTL compiler synthesis, using saed32nm tech libraries, but there are a lot of standard cell library files(.db .lib), I choose one of them but failed to perform the synthesis, saying the libraries do not have usable basic gates. Is this because I choose wrong library path and lib files or other reasons? My commands are as follows:
set_attribute hdl_search_path {./};
set_attribute lib_search_path {SEARCH PATH FOR LIB FILES};
set_attribute library [List LIBRARY_NAME.lib];

Hope someone could help me. Thanks very much!

Commands look OK. (Although you don't really need the ;'s and list command)

You say there are lots of libraries, are you sure you selected the right one? If you open the .lib in a text editor, can you see the basic gates you would expect? i.e. FFs, nand, nor etc? Or have you selected something like a clock gating or power gating library only?

jbeniston said:

Commands look OK. (Although you don't really need the ;'s and list command)

You say there are lots of libraries, are you sure you selected the right one? If you open the .lib in a text editor, can you see the basic gates you would expect? i.e. FFs, nand, nor etc? Or have you selected something like a clock gating or power gating library only?

Click to expand...

Actually I think the mistake is in the library file names. There are at least 50+ library files in the lib path, I really don't know which one is the correct, since I have viewed some but they don't seem to have basic gates description. If these files are in the same format, I don't think there is any usable for my script.

Do you have a list of filenames and sizes? Probably can take a guess.

There are two folders containing .db and.lib files, they are similar format such as : saed32rvt_pg_tt1p05v125c.lib sized from 2.3M to 2.4M. If I understand the meaning of the filename, I might be able to select a proper file among these similar lib files.

32 - 32nm
rvt - regular voltage threshold (lvt = low / hvt = high)
tt - Typical process (ss = slow / ff = fast)
1p05 - 1.05 volts
125c - 125 degress C

pg - I'd guess this means they are power gating cells, rather than standard cells, hence your problem. 2.4M sounds too small for a complete standard cell library

jbeniston said:

32 - 32nm
rvt - regular voltage threshold (lvt = low / hvt = high)
tt - Typical process (ss = slow / ff = fast)
1p05 - 1.05 volts
125c - 125 degress C

pg - I'd guess this means they are power gating cells, rather than standard cells, hence your problem. 2.4M sounds too small for a complete standard cell library

Click to expand...

Do you mean I need to list several lib files to form a complete standard cell library? By the way, could you please tell me what size a regular standard cell library is?

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jbeniston said:

32 - 32nm
rvt - regular voltage threshold (lvt = low / hvt = high)
tt - Typical process (ss = slow / ff = fast)
1p05 - 1.05 volts
125c - 125 degress C

pg - I'd guess this means they are power gating cells, rather than standard cells, hence your problem. 2.4M sounds too small for a complete standard cell library

Click to expand...

This file name have the most abbreviations: saed32rvt_ulvl/dlvl_ff0p85v125c/vn40c_i0p85v.lib. Could you please tell me the meaning? The two folders are named: db_ccs db_nldm

Yes, you may need to list several libraries, depending upon what you are doing.

The size of the library will vary, depending on how detailed the timing / power data is, and also how many cells there. I'd say at least 10MB, possibly up to 100MB for NLDM at 32nm.

CCS and NLDM are different ways of storing calculating timing information. CCS is more accurate, but bigger and slower NLDM. You only need to use one or the other.

jbeniston said:

Yes, you may need to list several libraries, depending upon what you are doing.

The size of the library will vary, depending on how detailed the timing / power data is, and also how many cells there. I'd say at least 10MB, possibly up to 100MB for NLDM at 32nm.

CCS and NLDM are different ways of storing calculating timing information. CCS is more accurate, but bigger and slower NLDM. You only need to use one or the other.

Click to expand...

Could you please tell me the meaning of the most complex filename: saed32rvt_ulvl/dlvl_ff0p85_v125c/vn40c_i0p85v.lib? Thanks very much!

Don't know. How do you get a filename with / in?

jbeniston said:

Don't know. How do you get a filename with / in?

Click to expand...

I'm sorry. That is an alternative filename. There are two kinds of filenames.
saed32rvt_ulvl_ff0p85v125c.lib
saed32rvt_dlvl_ff0p85vn40c_i0p85v.lib

Arthur Asimov Heinlein said:

I'm sorry. That is an alternative filename. There are two kinds of filenames.
saed32rvt_ulvl_ff0p85v125c.lib
saed32rvt_dlvl_ff0p85vn40c_i0p85v.lib

Click to expand...

They are level shifters. Do grep in the lib dir to see which file has most cell number.
grep cell\( *.lib
or
grep "cell (" *.lib

RCircuit said:

They are level shifters. Do grep in the lib dir to see which file has most cell number.
grep cell\( *.lib
or
grep "cell (" *.lib

Click to expand...

I have done the grep and find the file with most cell number.
[xyin1@cse-ws-12 db_nldm]$ grep -c "cell (" *.lib
saed32rvt_dlvl_ff0p85v125c_i0p85v.lib:24
saed32rvt_dlvl_ff0p85v125c_i1p16v.lib:24
saed32rvt_dlvl_ff0p85v25c_i0p85v.lib:24
saed32rvt_dlvl_ff0p85v25c_i1p16v.lib:24
saed32rvt_dlvl_ff0p85vn40c_i0p85v.lib:24
saed32rvt_dlvl_ff0p85vn40c_i1p16v.lib:24
saed32rvt_dlvl_ff0p95v125c_i0p95v.lib:24
saed32rvt_dlvl_ff0p95v125c_i1p16v.lib:24
saed32rvt_dlvl_ff0p95v25c_i0p95v.lib:24
saed32rvt_dlvl_ff0p95v25c_i1p16v.lib:24
saed32rvt_dlvl_ff0p95vn40c_i0p95v.lib:24
saed32rvt_dlvl_ff0p95vn40c_i1p16v.lib:24
saed32rvt_dlvl_ff1p16v125c_i1p16v.lib:24
saed32rvt_dlvl_ff1p16v25c_i1p16v.lib:24
saed32rvt_dlvl_ff1p16vn40c_i1p16v.lib:24
saed32rvt_dlvl_ss0p75v125c_i0p75v.lib:24
saed32rvt_dlvl_ss0p75v125c_i0p95v.lib:24
saed32rvt_dlvl_ss0p75v25c_i0p75v.lib:24
saed32rvt_dlvl_ss0p75v25c_i0p95v.lib:24
saed32rvt_dlvl_ss0p75vn40c_i0p75v.lib:24
saed32rvt_dlvl_ss0p75vn40c_i0p95v.lib:24
saed32rvt_dlvl_ss0p7v125c_i0p7v.lib:24
saed32rvt_dlvl_ss0p7v125c_i0p95v.lib:24
saed32rvt_dlvl_ss0p7v25c_i0p7v.lib:24
saed32rvt_dlvl_ss0p7v25c_i0p95v.lib:24
saed32rvt_dlvl_ss0p7vn40c_i0p7v.lib:24
saed32rvt_dlvl_ss0p7vn40c_i0p95v.lib:24
saed32rvt_dlvl_ss0p95v125c_i0p95v.lib:24
saed32rvt_dlvl_ss0p95v25c_i0p95v.lib:24
saed32rvt_dlvl_ss0p95vn40c_i0p95v.lib:24
saed32rvt_dlvl_tt0p78v125c_i0p78v.lib:24
saed32rvt_dlvl_tt0p78v125c_i1p05v.lib:24
saed32rvt_dlvl_tt0p78v25c_i0p78v.lib:24
saed32rvt_dlvl_tt0p78v25c_i1p05v.lib:24
saed32rvt_dlvl_tt0p78vn40c_i0p78v.lib:24
saed32rvt_dlvl_tt0p78vn40c_i1p05v.lib:24
saed32rvt_dlvl_tt0p85v125c_i0p85v.lib:24
saed32rvt_dlvl_tt0p85v125c_i1p05v.lib:24
saed32rvt_dlvl_tt0p85v25c_i0p85v.lib:24
saed32rvt_dlvl_tt0p85v25c_i1p05v.lib:24
saed32rvt_dlvl_tt0p85vn40c_i0p85v.lib:24
saed32rvt_dlvl_tt0p85vn40c_i1p05v.lib:24
saed32rvt_dlvl_tt1p05v125c_i1p05v.lib:24
saed32rvt_dlvl_tt1p05v25c_i1p05v.lib:24
saed32rvt_dlvl_tt1p05vn40c_i1p05v.lib:24
saed32rvt_ff0p85v125c.lib:350
saed32rvt_ff0p85v25c.lib:350
saed32rvt_ff0p85vn40c.lib:350
saed32rvt_ff0p95v125c.lib:350
saed32rvt_ff0p95v25c.lib:350
saed32rvt_ff0p95vn40c.lib:350
saed32rvt_ff1p16v125c.lib:350
saed32rvt_ff1p16v25c.lib:350
saed32rvt_ff1p16vn40c.lib:350
saed32rvt_pg_ff0p85v125c.lib:20
saed32rvt_pg_ff0p85v25c.lib:20
saed32rvt_pg_ff0p85vn40c.lib:20
saed32rvt_pg_ff0p95v125c.lib:20
saed32rvt_pg_ff0p95v25c.lib:20
saed32rvt_pg_ff0p95vn40c.lib:20
saed32rvt_pg_ff1p16v125c.lib:20
saed32rvt_pg_ff1p16v25c.lib:20
saed32rvt_pg_ff1p16vn40c.lib:20
saed32rvt_pg_ss0p75v125c.lib:20
saed32rvt_pg_ss0p75v25c.lib:20
saed32rvt_pg_ss0p75vn40c.lib:20
saed32rvt_pg_ss0p7v125c.lib:20
saed32rvt_pg_ss0p7v25c.lib:20
saed32rvt_pg_ss0p7vn40c.lib:20
saed32rvt_pg_ss0p95v125c.lib:20
saed32rvt_pg_ss0p95v25c.lib:20
saed32rvt_pg_ss0p95vn40c.lib:20
saed32rvt_pg_tt0p78v125c.lib:20
saed32rvt_pg_tt0p78v25c.lib:20
saed32rvt_pg_tt0p78vn40c.lib:20
saed32rvt_pg_tt0p85v125c.lib:20
saed32rvt_pg_tt0p85v25c.lib:20
saed32rvt_pg_tt0p85vn40c.lib:20
saed32rvt_pg_tt1p05v125c.lib:20
saed32rvt_pg_tt1p05v25c.lib:20
saed32rvt_pg_tt1p05vn40c.lib:20
saed32rvt_ss0p75v125c.lib:350
saed32rvt_ss0p75v25c.lib:350
saed32rvt_ss0p75vn40c.lib:350
saed32rvt_ss0p7v125c.lib:350
saed32rvt_ss0p7v25c.lib:350
saed32rvt_ss0p7vn40c.lib:350
saed32rvt_ss0p95v125c.lib:350
saed32rvt_ss0p95v25c.lib:350
saed32rvt_ss0p95vn40c.lib:350
saed32rvt_tt0p78v125c.lib:350
saed32rvt_tt0p78v25c.lib:350
saed32rvt_tt0p78vn40c.lib:350
saed32rvt_tt0p85v125c.lib:350
saed32rvt_tt0p85v25c.lib:350
saed32rvt_tt0p85vn40c.lib:350
saed32rvt_tt1p05v125c.lib:350
saed32rvt_tt1p05v25c.lib:350
saed32rvt_tt1p05vn40c.lib:350
saed32rvt_ulvl_ff0p85v125c_i0p85v.lib:12
saed32rvt_ulvl_ff0p85v25c_i0p85v.lib:12
saed32rvt_ulvl_ff0p85vn40c_i0p85v.lib:12
saed32rvt_ulvl_ff0p95v125c_i0p95v.lib:12
saed32rvt_ulvl_ff0p95v25c_i0p95v.lib:12
saed32rvt_ulvl_ff0p95vn40c_i0p95v.lib:12
saed32rvt_ulvl_ff1p16v125c_i0p85v.lib:12
saed32rvt_ulvl_ff1p16v125c_i0p95v.lib:12
saed32rvt_ulvl_ff1p16v125c_i1p16v.lib:12
saed32rvt_ulvl_ff1p16v25c_i0p85v.lib:12
saed32rvt_ulvl_ff1p16v25c_i0p95v.lib:12
saed32rvt_ulvl_ff1p16v25c_i1p16v.lib:12
saed32rvt_ulvl_ff1p16vn40c_i0p85v.lib:12
saed32rvt_ulvl_ff1p16vn40c_i0p95v.lib:12
saed32rvt_ulvl_ff1p16vn40c_i1p16v.lib:12
saed32rvt_ulvl_ss0p75v125c_i0p75v.lib:12
saed32rvt_ulvl_ss0p75v25c_i0p75v.lib:12
saed32rvt_ulvl_ss0p75vn40c_i0p75v.lib:12
saed32rvt_ulvl_ss0p7v125c_i0p7v.lib:12
saed32rvt_ulvl_ss0p7v25c_i0p7v.lib:12
saed32rvt_ulvl_ss0p7vn40c_i0p7v.lib:12
saed32rvt_ulvl_ss0p95v125c_i0p75v.lib:12
saed32rvt_ulvl_ss0p95v125c_i0p7v.lib:12
saed32rvt_ulvl_ss0p95v125c_i0p95v.lib:12
saed32rvt_ulvl_ss0p95v25c_i0p75v.lib:12
saed32rvt_ulvl_ss0p95v25c_i0p7v.lib:12
saed32rvt_ulvl_ss0p95v25c_i0p95v.lib:12
saed32rvt_ulvl_ss0p95vn40c_i0p75v.lib:12
saed32rvt_ulvl_ss0p95vn40c_i0p7v.lib:12
saed32rvt_ulvl_ss0p95vn40c_i0p95v.lib:12
saed32rvt_ulvl_tt0p78v125c_i0p78v.lib:12
saed32rvt_ulvl_tt0p78v25c_i0p78v.lib:12
saed32rvt_ulvl_tt0p78vn40c_i0p78v.lib:12
saed32rvt_ulvl_tt0p85v125c_i0p85v.lib:12
saed32rvt_ulvl_tt0p85v25c_i0p85v.lib:12
saed32rvt_ulvl_tt0p85vn40c_i0p85v.lib:12
saed32rvt_ulvl_tt1p05v125c_i0p78v.lib:12
saed32rvt_ulvl_tt1p05v125c_i0p85v.lib:12
saed32rvt_ulvl_tt1p05v125c_i1p05v.lib:12
saed32rvt_ulvl_tt1p05v25c_i0p78v.lib:12
saed32rvt_ulvl_tt1p05v25c_i0p85v.lib:12
saed32rvt_ulvl_tt1p05v25c_i1p05v.lib:12
saed32rvt_ulvl_tt1p05vn40c_i0p78v.lib:12
saed32rvt_ulvl_tt1p05vn40c_i0p85v.lib:12
saed32rvt_ulvl_tt1p05vn40c_i1p05v.lib:12

Have you tried saed32rvt_ss0p95v125c.lib? Looks the most likely.

jbeniston said:

Have you tried saed32rvt_ss0p95v125c.lib? Looks the most likely.

Click to expand...

Well I tried saed32rvt_tt1p05v125c.lib and successfully come out with the RTL report using RTL compiler. Now the problem is that I would like to convert the schematic of my design which is generated in RTL compiling to netlist, but I don't know how to add this library file into Cadence library manager, so I cannot take a look at the schematic of the cells in this file using icms&.

RTL compiler has a schematic viewer, so you should be able to use that.

You need the Open Access libraries, rather than .libs for Cadence IC.

jbeniston said:

RTL compiler has a schematic viewer, so you should be able to use that.

You need the Open Access libraries, rather than .libs for Cadence IC.

Click to expand...

Then is there any method for me to get Open Access libraries? It seems there are a lot of necessary files.

- - - Updated - - -

jbeniston said:

RTL compiler has a schematic viewer, so you should be able to use that.

You need the Open Access libraries, rather than .libs for Cadence IC.

Click to expand...

Cadence IC could import the structural file of my design as schematic view, then I could get use of this schematic view, converting it into netlist. But now the problem is the compiler library.

Arthur Asimov Heinlein said:

It seems there are a lot of necessary files.

Click to expand...

Welcome to IC design

RTL Compiler while synthesis requires at least one basic gate i.e. inverter or buffer or and, nand to implement the logic.
This is a checj it usually does to avoid failures larter. If this is teh Error you see you need to add a standard cell lib which has these cells that are usable for technology mapping.