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how to define generated clock in DC?

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jinruan

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dc get_pins

hi guys
i can't define my generated clock in DC, what's the reason?
for example, clk_i is the input clock, and clk_o is the internal clock which was divided 256 by clk_i.

i use the following command
create_generated_clock {freq_div/clk_o} -name clk_o -source clk_i -divide_by 256

but the result indicate that it can't find clk_o in the top design and the command failed.
 

how to define generated clock

Hi, my dear friend.
You should set generated clock like this:
create_generated_clock -edges {first_edge second_edge last_edge} \
-source [get_ports clk_i] [get_pins clk_o]
1. must specify the pin name to generate a clock.
2. Don't specify a clock name. This is the reason that your setting get a error in DC.
 
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    Anklon

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how to define a clock generated by two clocks

you should use [get_pins frq_div/clk_o].
 

clk_o

ok, i think it's so
but the error indicate that freq_div/clk_o can't be
searched in the top design.
as documented says, the global variable "access_internal_pins" must be true to enable pin access(the default is false), but i can't find the .synopsys_dc.setup"files in $SYNOPSYS install directory, (it's so strange,my OP is Unix sparcos5).
 

synopsys generated clock

The .synopsys_dc.setup file can be write by yourself. So you can modify this variable in your .synopsys_dc.setup file.
 

i have define the variable in my .synopsys_dc.setup file as below:
access_internal_pins="true",
but i still can't find nets or pins in submodule.
 

try this
get_pins freq_div/clk_o

if can not find this pin, only the path is not right.
 

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