wearty
Newbie level 2
Apologies for a non-technical post. Currently I am working as a fpga prototyping engineer.
My job is to synthesize RTL, place and route , meet timing and provide this bit file to the emulation team.
RTL is the input we get and bit file is the output or deliverable we need to provide to the next team.
I feels like most of the work is done by the tools and there is very little left for us to do.
I would like to do RTL logic design. Will it be possible to shift to that domain with my present experience?
My job is to synthesize RTL, place and route , meet timing and provide this bit file to the emulation team.
RTL is the input we get and bit file is the output or deliverable we need to provide to the next team.
I feels like most of the work is done by the tools and there is very little left for us to do.
I would like to do RTL logic design. Will it be possible to shift to that domain with my present experience?
