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Which mix-library (HVt and LVt) synthesis is better?

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ivlsi

ivlsi

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Hi All,

There are several approaches regarding mix-library (HVt and LVt)synthesis

Approach#1: synthesize all your design with HVt lib and only then optimize critical paths with LVt cells

Approach#2: give to the tool all your libraries and it will do its best to meet timing, area and power.

What approach is best and why?

Thank you!
 

Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?

Hi,

My point is
Approach#1: This is good for Low Frequency and low-power designs.
Approach#2: This approach is good for high frequency designs.

This will be my approach. Let us discuss some more on this.
 

Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?

Okay let's discuss :)
 

Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?

Approach 1 is better....
 

Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?

You need to decide the trick of the trade depending on your requirements. If you highly leaky design better go for all HVT and if you have a timing critical design where you can compromise a bit on the leakage go for LVT.

However you can go for SVT/RVT cells to converge on both leakage and timing to some extent. What is the process node you're using?
 

Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?

The process is 40LP (40nm low power)
 

Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?

If you can meet timing/power in prelayout, use all HVT then. Otherwise use mix mode, some time back end would be pissed off if you give them netlist not meeting timing.
 

Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?

If you don't have any timing violations (in high frequency designs if the WNS of violations are less than 3% of clock period it can be fixed in layout as skew comes in picture) in your design, you can do synthesis only with HVT.

If there are any timing issues you can open either LVT during incremental synthesis or at the starting itself. But if you are opening LVT at the start of synthesis, then there has to be constrained imposed on the design related to power so that less number of LVT cells will be used.

In case of RTL compiler there are specific attributes which can be used for minimizing the usage of LVT cells even if LVT is opened at the start of synthesis.
 

Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?

vamsi1255 said:
In case of RTL compiler there are specific attributes which can be used for minimizing the usage of LVT cells even if LVT is opened at the start of synthesis.
Click to expand...

Do you know what are the attributes?
 

Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?

ivlsi said:
Do you know what are the attributes?
Click to expand...

Following attributes can help you out

lp_multi_vt_optimization_effort which can control usage of LVT.
power_optimization_effort which can control usage of LVT at the cost of area.

These are provided in RTL compiler attributes pdf file.
 
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    ivlsi

    ivlsi

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Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?

Thank you!
 

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