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FPGA asynchronous set and reset

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shaiko

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An asynchronous reset gives '0' at the output of a DFF, while an asynchronous set gives '1' at the output of a DFF.
Do all FPGA's feature an asynchronous set and reset for their DFFs?
Are there any devices that support only an asynchronous reset?
 

FPGAs from Altera and Xilinx do have multiple types of D-Flip Flops namely:

1. FDCE - D-FF with Asynchrounous Clear (C)
2. FDRE - D-FF with Synchronous Reset (R)
3. FDSE - D-FF with Synchronous Set (S)
4. FDPE - D-FF with ASynchronous Preset (P)

# To implement a FF with Asynchronous Reset, the Tool will infer FDCE and connect the reset pin to the Clear Pin of the FDCE.
# To implement a FF with Synchronous Reset only an FDRE will be inferred (used)
 
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    shaiko

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What DFF will be inferred with this code:

Code: 
process ( clock , reset , set ) is
begin
if reset  = '1' then  
y <= '0' ;
elsif set = '1' then
y <= '1' ;
elsif rising_edge ( clock ) then
y <= x ;
end if;
end process ;
 

Your code will infer a transparent latch along with FDCE. But the tool will complain since both set and reset are asynchronous. The design may not also work on the FPGA.

If you restructure your code this way, you will infer only a single FDCE.
Code: 
process ( clock, reset ) 
begin
  if reset  = '1' then  
     y <= '0' ;
  elsif rising_edge ( clock ) then
     if set = '1' then
        y <= '1' ;
     else
        y <= x ;
     end if;
  end if;
end process ;
 
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    shaiko

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It can depend what family you are using. I only have experience with ALtera, but the older devices have both an async reset and preset. So your reset/set code may infer a register here. But newer devices just have a single reset with a single entry point, allowing async reset or preset (via not-gate push back), so will only allow a single async signal in the code.
 
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Spartan 3 FPGAs have FFs with synch set, reset. The same code on the spartan 3 FPGA will give a single DFF (FDRS). While on the Virtex 6 will infer LUT along with a FDCE.

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity example_FDRSE is
   port(
      Q : out std_logic;      -- Data output
      CLK :in std_logic;      -- Clock input
      RESET :in std_logic;  -- Synchronous reset input
      D :in  std_logic;      -- Data input
      SET : in std_logic   -- Synchronous set input
   );
end example_FDRSE;
architecture Behavioral of example_FDRSE is  --architecture of the circuit.
begin 
process(CLK) 
begin  
  if ( rising_edge(CLK) ) then  --This makes the process synchronous(with clock)
    if (RESET = '1') then
         Q <= '0';
     else
           if(SET = '1') then
             Q <= '1';
           else
             Q <= D;      
           end if;
      end if;
  end if;      
end process;  --end of process statement.
end Behavioral;
This code on Spartan series yields a single FDRS while on the Virtex yields a FDCE along with LUT.
 
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