Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[STA] Propagation Delay over cells & NLDM tables

Status
Not open for further replies.
ivlsi

ivlsi

Advanced Member level 3
Advanced Member level 3
Joined
Feb 17, 2012
Messages
883
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,868
Hi All,

As far as I know, Propagation Delays over the STD cells are calculated using the NLDM tables. But, in which phase - during logic synthesis (Pre-P&R) or during P&R or in both cases?

Thank you!
 

Hi ivlsi,

STD cells are blackboxes for synthesizer and for P&R tools. They're usually described as separate timing-power model with NLDM tables (or with extensions - CCS, ECSM) and geometric abstract information for P&R tools. Each STA tool uses propagation delays from timing library regardless of project stage - pre- or layout stage. The difference in timing calculation at the synthesis stage and layout stage is that in synthesis stage there are no information about interconnections between cells and timing calculation is based on wireload models or something like that. But at the layout stage it is possible to extract parasitic values and obtain more accurate data.

Hope it was helpful.

Best regards,
Kuxx.
 
Both Pre and Post Layout , Delay calculation is used.

why Delay Calculation in Pre - Layout stage?.
-To get the information about any violations in the library and to fix it in the first place. Definitely this will not cover all the parasitic information and hence the information will not be accurate. But using this will help to eliminate few errors in the early stage.

Delay calculation in Post Layout stage?.
This will have the information on Parasitic and interconnect delay.

Hence the Calculation is done in both the process stage.

Thank you,
Prashanth M
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top