Question regarding Le files and captable files

Hi,

I have some basic questions regarding synthesis:

What is the basic difference between wire load model, RC- PLE model and RC-P model used for synthesis. ?
What do LEF files and Captable files comprise of ? and how the timing is calculated with these files.

Thanks
limitless

Hi,

the differences in the 3 models of synthesis:
Wire load model:
This models gives a vague information about R and C values for a given area and fan-out of the cells
RC-PLE:
This models needs LEF of std_cells, memories and IPs and captables of particular corner. From LEF we have the dimensions and area of the std_cells, memories. And from captables we have R and C of nets for given length of the nets.
from this tool calculates the RC and C values.
RC-P:
you have to give the DEF of block for which you are synthesizing. DEF has dimensions of the block, placement information, port information of the block.
So the synthesis tool will have more data of the block. From this the assumptions of the synthesis tool reduced and results are closer to the PnT tool.

Am i clear?

Hi,

If we don't use any wire-load model or PLE flow then synthesis tool will consider zero cap and zero resistance for nets in the design.

1) Synthesis using wire-load models

Wire-load models are based on your gate count and fan-out. You assign certain amount of cap, resistance values to the nets which will help your synthesis tool for better optimization.

2) Synthesis using PLE flow

RC values for a net are taken from your technology lef file or cap table file which is loaded into the synthesis tool. Synthesis tool algorithms estimates the lengths of the nets and assigns the R & C values for technology files.

3) Synthesis using Physical flow

The RC-Physical flow uses in addition to PLE flow, a complete placement and congestion during the RTL-to-gates phase, to create a better netlist.

All the above flows are developed to take care of net delays arise at layout end.

~vamsi