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hSpice Simulation takes long time

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jay496

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Hi,

I am working on ADC. As a part I designed a counter using T_Flip Flop.
Initially I tried designing a 3bit counter it took 25min to simulate, my requirement is a 8bit counter.
I tried designing a 6bit and 8bit counter both of them the simulation time is very long.

6bit counter :: simulation time 6hours

8bit counter :: simulation time more than 8hours

Is there any issue with convergence or any other issue how could I know.??

Thanks,
Jay
 

First, make sure that every bistable element has an
explicit initialization. If it's a POR then you have to
ramp the supply. A master reset for simulation purposes
can be a good idea - although if not implemented in the
final design, you may propagate a false confidence in
testability.

You cannot solve, a priori, a circuit with two valid states.
Let alone 2^N. TFFs are that.

You may receive a solution, of course. But the validity
wants checking, and may be totally different with any
change to conditions (FFs initializing on leakage balance
are not very predictable, nor predictions very well tied
to eventual reality).
 

Hi dick_freebird,

Thanks for the reply I am beginner in this could you please elaborate,


Please Find the Attached files of the source code of 3bitCounter

and its output log file & .st0 file

Main thing
My design is by using CNFETS I have Downloaded PTM files from Stanford university.

If I replace the CNFETS with Normal CMOS the simulation time of
3bitcounter is less than 3seconds and for a 8bitcounter harldy 2min(CNFET more than 9 hours :(( )


Thanks,
Jay
 

Attachments

  • CNFET.txt
    137.3 KB · Views: 149
  • PARAMETERS.txt
    6.1 KB · Views: 128
  • 3bitcmos.out.txt
    40.5 KB · Views: 126
  • 3bitcmos.st0.txt
    2.4 KB · Views: 141
  • 32nm_HP.txt
    11 KB · Views: 147
  • 3bitCounter.out.txt
    9.6 KB · Views: 153
  • 3bitCounter.sp.txt
    1.3 KB · Views: 146
  • 3bitCounter.st0.txt
    2.5 KB · Views: 139

usually convergence is one of issues that cause long time. one of ways for solving this problem is:
use a parallel capacitor with nonlinear elements.
 

Check your hokey CNFET model for issues like no values
for terminal-terminal capacitances, insanely low series
resistances etc. - especially if you are seeing timestep
warnings. If these are supposed to be really fast devices
then you may have to force a timestep maximum that
will not let the simulator step past an edge when upranged -
you can't do a decent Newton iteration across a bistable
event. Of course this will cost you solution speed as well,
during the "quiet" intervals you'll still be solving fine grained.

Some simulators have a CMIN value for transient, similar
to GMIN for DC solution, which can be useful "ballast"
against numerical thrashing with unrealistically fast devices.
 
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    jay496

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@an_82

It helped me somehow but still simulation time quite high...
it took some 20 to30 min less compared to my prior time(6hrs)

- - - Updated - - -

@dick_freebird

I have gone through the log I cant see any warnings w.r.t timestep...

only warning I faced is **warning** associated with encrypted blocks were suppressed due to encrypted content

and a diagnostic **diagnostic** rebuilding matrix without pivot option
 

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