Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Use of inverters in CTS flow

Status
Not open for further replies.
R

ramesh28

Member level 3
Member level 3
Joined
May 21, 2013
Messages
57
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,670
Hello all,

Can anyone explain me that while building CTS, can we use buffer only or inverter and buffer both?

Bcz in my pnr tool (Olympus SOC), default setting of use of inverter is false in run_auto_cts command? so i have doubt that before running this command, can i enable use of inverter argument? OR can i go with buffer only?

what is preferable use of buffer only or both? And why? considering delay and power dissipation.

Thank you..
 
Last edited:

Very nice but off-the-track reply removed :)
 
Last edited:

Hey myshkinuk,

i am talking about CTS means clock tree synthesis in pnr flow..
 

Heh - same trouble - different signal :)

Should have spotted the forum name.

This place is noobs and gurus all mixed up!
 

ramesh28 said:
Hello all,

Can anyone explain me that while building CTS, can we use buffer only or inverter and buffer both?

Bcz in my pnr tool (Olympus SOC), default setting of use of inverter is false in run_auto_cts command? so i have doubt that before running this command, can i enable use of inverter argument? OR can i go with buffer only?

what is preferable use of buffer only or both? And why? considering delay and power dissipation.

Thank you..
Click to expand...


You can use both, not an issue unless you end up in inverting the clock phase. Using inverters helps in reducing the area requirement, hence preferred in congested designs.

Regards
Jeevan
 
Thanx for reply Jeevan.

Use of inverter is preffered in congested design in that case if i dont have congestion and area requirement, but my main concern is about reducing delay and achieving better timing. so still i go with both (inverter and buffer) or i prefer to use only buffer?
 

ramesh28 said:
Thanx for reply Jeevan.

Use of inverter is preffered in congested design in that case if i dont have congestion and area requirement, but my main concern is about reducing delay and achieving better timing. so still i go with both (inverter and buffer) or i prefer to use only buffer?
Click to expand...

Buffer has higher delay inherently as it is nothing but back to back inverters by design. You can go with the buffer-inverter flow, but please make sure that the clock phases are as per requirement.

Regards
Jeevan
 

    V

    Points: 2
    Helpful Answer Positive Rating
What I have observed is that a single buffer delay is not exactly two buffers delay.
So if u need less delay and less power dissipation then u go for more buffers.
If u need good slew and better pulse width invs will be the good choice.

Normally the tool adds buffers at the root and invs at the clock pins of the flops.
This I feel is the good approach.
 

    V

    Points: 2
    Helpful Answer Positive Rating
Thank you guys..really nice explaination.

pavanks said:
What I have observed is that a single buffer delay is not exactly two buffers delay.
So if u need less delay and less power dissipation then u go for more buffers.
If u need good slew and better pulse width invs will be the good choice.

Normally the tool adds buffers at the root and invs at the clock pins of the flops.
This I feel is the good approach.
Click to expand...

Hello pavanks,
you mean to say that single buffer delay is not exactly two inverter delay, am i right?

And can you tell me that how inverters help in improving, i mean achieving good skew and better pulse width? As buffer itself also contains two inverters only.
 

I meant slew not skew.
Slew is transition.

If u have good rise and fall transition the pulse width will be maintained and will not be chipped.
 

If you use buffers then skew will be high. You can also use inverters, but total number of inverters from clock definition point to clock pin of the FF should be even.

Make sure that the buffers or inverters which you are using in clock tree should have balanced rise and fall times. (i.e, RIse delay ~= Fall Delay ). Otherwise the pulse width of the clock signal will decreased and it will fail the functionality od design.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top