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Hold violation on clock gating path

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ramesh28

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Hello all,

How hold violation is taken care of if it is on clock gating path?
Which are the reasons because of hold violation occurs on clock gating path?

Can we fix it manually by adding buffers?

Reply,

Thank you..
 

The clock gating hold violation is usually because: the clk_gate_enb reach the gating cell too fast than the clock signal.
So, of cause you can add buffer on the clk_gate_enb path to eliminate the hold violation.
(Assume the clk_gate_enb and clock signal are SYNC to each other)
 
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