Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] ROM implementation on FPGA

Status
Not open for further replies.
Did you find the datasheet pdf that goes with that ip core? It usually mentions how to provide initial values and such.
 
If you're using Xilinx IP, then when you generate the IP core using coregen, you can add the initial values via the coregen itself. You may need the values in a hex format or any other one specified by Xilinx. You can get this information from the ISe user guide as well as the cores user guide.
 
When you are generating the IP, there is an option to load the initial values which are in a *.ini or *.hex file.
You can choose the file (the data width and depth need to take care) and load the data.
 
With Altera Quartus II, a ROM is instantiated with a Megafunction. An "mif" file is commonly used to specify the contents and defined as a parameter for the ROM.
 
when you define block ram with coregen, you can put a file with coe extension for initial value. there is a similar way for rom.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top