Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

while fixing the setup violation for one path, other paths gets affected

Status
Not open for further replies.
R

ramesh28

Member level 3
Member level 3
Joined
May 21, 2013
Messages
57
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,670
hello all,

while fixing the setup violation for one path, other paths gets affected means when i'm reduced slack of maximum violated path from -800ps to -600ps, but i observed that another path's slack violation goes to -950ps.

why this is happening?

i'm trying to swap cell means upsizing cells from data path to reduce delay.

please, give some idea why this is happening. i'm beginner to timing violation fixing.

what precaution i have to taken while fixing setup violation?
 

Hi ramesh,

The reason is there will be cells present in both paths so that its violation. we can easily pick that cells by fanout if the fanout is high it will affect other paths too.. So upsize or downsize the cells which is independent to that path. Also look the path is from which clock to which clock(whether it can be set to false path or multicyle path) .

To fix this setup violation.
if its reg to reg path try to add buffers on the clock pin.
in to reg or reg to out or in to out delete unwanted buffers.
 
vijayR15 said:
Hi ramesh,

The reason is there will be cells present in both paths so that its violation. we can easily pick that cells by fanout if the fanout is high it will affect other paths too.. So upsize or downsize the cells which is independent to that path. Also look the path is from which clock to which clock(whether it can be set to false path or multicyle path) .

To fix this setup violation.
if its reg to reg path try to add buffers on the clock pin.
in to reg or reg to out or in to out delete unwanted buffers.
Click to expand...

Hello Vijay,

Thanx for reply.. you means that no need to touch the (upsize or downsize) cell which has high fanout. is this right?

you saying that for fixing setup violation of reg2reg path, try to add buffers on the clock pin but i heard that adding buffers to clock path is not a good choice until unless we dont have other choice. and it also affect the clock skew. if i'm wrong please correct me.
 

Hi ramesh28,
At which step did you try to fix the setup, synthesis/placement/...
Regards.
 

rca said:
Hi ramesh28,
At which step did you try to fix the setup, synthesis/placement/...
Regards.
Click to expand...

Hi,

I'm fixing setup after post routing stage. I know that setup has to fix at placement stage but after cts i found that setup getting disturbed.

so please suggest solution that how to fix it.?
 

So, you mean the setup is always met till CTS step?
And after CTS step, the post-CTS optimisation setup does not able to fix the setup?
Do you "reduce" the setup margin during the optimisation post route stage versus the margin used during the placement?
 

in my case some setup violations still there, not completely met at placement stage.

is setup always met till CTS, is this possible all time? or without fixing all setup violation at placement stage, can we go to CTS? if it is not achievable.

what is setup margin means?
 

In encounter during placement optimisation, the tool add by itself 100ps of margin and the user could add the margin he wants to over constraint the tool to fix the setup.
setup margin is additional marge added to the current setup target, means force the tool to force not to reach 0ps, but the margin as target.
 
ok. that means, setup margin is more then it show more setup violations. and if we reduce it then overall setup violations also reduces.

so setup margin added by tool initially to achieve better timing results. is this right?

Is this similar to clock uncertainity?
 

right,
clock incertainty could be also considered as additional margin.
 
Hi ramesh,

u can upsize or downsize the high fanout cell. but keep this as a last priority to use. The key point is consider if it has 2 fanout it will have effect in 2 paths. If it has more paths it will have impact on more path.

yes u r right with reg2reg violation but in some case there will no way to optimize other than adding few buffer in clock in that case we can go ahead that will not affect much.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top