Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Yes, if your FPGA family support differential I/O-standards, e.g. LVDS. Review the online help or user manual of your design tool how to specify differntial pins in IO constraints,
There seems to be a fundamental difference between Altera and Xilinx about differential I/O.
In Altera, you can have a single-ended port in the top level entity and tell the place&route tools that it should be mapped to a differential transmitter/receiver.
I Xilinx, you must have both the '+' and the '-' signals as ports in the top level entity and connect them to a differential transmitter/receiver in your source code.
If you are using lattice (i have used ECP2), then no need to map the pin_n and pin_p separately.
Means in your top design module, you need to consider only one port (positive), then in the *.lpf you need to mention that the port is LVDS.
Then automatically the negative pin will assign the inverted value.
- - - Updated - - -
For lvds i think LVDS25 (2.5V), LVDS33(3.3V), etc are there, you can chose what you need (Depends upon the frequency of operation)
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
