problems using wider metal width

Hi,

What problems we face if we put wider metal width instead of multiple metal tracks ?

How is it related to EM ?

Please HELP !!!

Thanks and Regards,

Electromigration lifetime is inverse to current density
and current density, inverse to width.

You will encounter limits on conductor width in any
modern fab, and will have to slot or space to meet
them.

Wider metal is more area-efficient than multiple
narrower stripes of equal total width.

The spacing of metal to "wide metal" is often larger
than basic spacing rules. This can impact layout to
some small extent. I tend to lay out lines at the
"wide metal" threshold minus 0.1 - 1um in low level
bussing. There will be some cases where two not-
wide lines will carry more current in the same area
(net width inclusing spacings) than one "wide" one
of equal conductor cross-section. Not too many,
but some (right about, and up to 2X the "wide"
threshold).

Supposedly if your metal line becomes narrower than
metal grain size, electromigration improves markedly.
But you will not know this grain size, and the foundry's
control of it, in all likelihood.

Thanks a lot dick_freebird.

If there are two scenario to use metal width
a> 5um
b> 5 slotted metals of 1um each


The problem using a big fat 5um is
1. increases capacitance. RC time constant will not decrease.
2. To avoid the polishing irregularities and making the etch rate variation continuous.
3. if metal width is wider than metal grain size, EM gets effected. resistance to EM decreases.

Please correct if I am wrong and please add any additional points if am missing.

Your capacitance is liable to be worse with the 5x1 scheme.

The w=5 has 5*L plate area and 2*L*? fringing capacitance.
The 5*w=1 has 5*L plate area and 10*L*? fringing - more
edges.

Linewidth reduction may also make your w=5 line into w=4.8
(if dW=-0.2u) while the 5*1 becomes 5*0.8 (w=4). You don't
know what your lot will come out like or the linewidth
distribution, in all likelihood.

CMP ought not to affect the metal, only the ILDs. At least
I've never heard of people ginding off metal - very messy.

Thanks dick_freebird for correcting.


But, could you please let me know

what problems i will face if I use a single 5um metal width [if foundry threshold max limit 1um ] ?

From the above discussion, I got two points :

1. if metal width is wider than metal grain size, EM gets effected. resistance to EM decreases.

2. The spacing of metal to "wide metal" is often larger than basic spacing rules. This can impact layout to
some small extent.

Any Important point that am missing...please help !!!

Thanks and Regards,

Hi,
What is metal grain size ?

@vinodhsaminathan : its a general doubt.

for example :

If there are two scenario to use metal width
a> 5um
b> 5 slotted metals of 1um each

grain metal size is 1um.

What problems we will face if we use a big fat 5um metal ? Please help !!!

U will get a very high parasitic capacitance. since c directly proportional to width. sometim cross talk also.

rameshiloveu said:

What problems we will face if we use a big fat 5um metal ?

Click to expand...

Probably you won't get a clean DRC .

I think wide metals are prohibited by DRC because of manufacturability considerations:

1. mechanical stability: wide metals are delaminated more easily than narrow metals - and thus metals have to have slots (openings), or layed out as multiple parallel narrow lines.
2. CMP: wide metals are subject to dishing (thinning) because of CMP - chemical-mechanical polishing:

https://www.google.com/url?sa=t&rct...2dd2Z-wh10gTRDg&bvm=bv.53371865,d.aWc&cad=rja

An additional advantage of multiple lines versus one wide line is current ballasting - where current is distributed more uniformly over the width of the metal line. In wide metals, metal bends and turns will create areas of very high current density at the bend/turn points - this may be avoided or suppressed in case of multiple metal lines.

Wide metal lines = higher cap as previously stated. Bear in mind that this may result in higher peak currents / possible EMI issues / etc.