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Which one is better?

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rezvania

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Hi. In VHDL code to assign a signal to output port, which one is better: Out of process or after than the signal update in process?
for example:
...
dout : out std_logic _vector(7 downto 0);
...
signal s1 : std_logic _vector(7 downto 0);

process(clk,rst)
begin
.
.
.
s1 <= s1 + '1' ;
? dout <= s1;
.
.
.
end process;
? dout <= s1;
 

they are both different.
outside the process will create a wire, inside a clocked process will create a register. So there isnt a better one, it depends what you want.

PS. s1 <= s1 + '1';
That is not standard VHDL. You cannot do arithmatic with std_logic_vectors.
 

Thank you but:
1- when you implement scheme on FPGA, dout is connect to out ports. Is there difference between wire or register? Is different delay or etc?
2- if s1 was a counter, it can't be std_logic_vector? it just increase with clock. If std_logic_vector is not standard VHDL code, what is standard of it?
 

1. A register adds a 1 clock pipeline delay
2. You're probably using the std_logic_unsigned/signed library which allows you to do arithmatic with std_logic_vectors. This is not part of the VHDL standard. You should use the numeric_std and signed/unsigned types instead.
 

TrickyDicky said:
1. A register adds a 1 clock pipeline delay
2. You're probably using the std_logic_unsigned/signed library which allows you to do arithmatic with std_logic_vectors. This is not part of the VHDL standard. You should use the numeric_std and signed/unsigned types instead.
Click to expand...

In first post, when clk raises s1 increases and immidiately dout (out of process) has change. but dout (in process) change after delta second and new s1 assign to dout in process. so both of them occure in one clock not by 1 clock delay.
do you agree with me?

if I want to use just unsigned arithmatic, can I use std_logic_vector with unsigned library?
thank you
 

but dout (in process) change after delta second and new s1 assign to dout in process. so both of them occure in one clock not by 1 clock delay.
Click to expand...

"new s1 assign to dout in process" is NOT true.
in a rising_edge(clk) all statements inside if takes place.
then S1 change to new (S1+1) after delta time and sync with it dout changes to S1 after delta time.

consider this 2 codes below. result is same for both
Code: 
process(clk)
begin
if rising_edge(clk) then
   dout <= s1;
   s1 <= s1 + 1 ;
end if;
end process;

Code: 
process(clk)
begin
if rising_edge(clk) then
   dout <= s1;
   s1 <= s1 + 1 ;
end if;
end process;
 

rezvania said:
In first post, when clk raises s1 increases and immidiately dout (out of process) has change. but dout (in process) change after delta second and new s1 assign to dout in process. so both of them occure in one clock not by 1 clock delay.
do you agree with me?
Click to expand...

No. s1 is updated to s1+1, and dout is updated to s1 (The old value, not s1+1). Hence it is 1 clock cycle behind s1. This is the rules for signals, as they are not updated until a process suspends. There is no delta delay as they are both updated simultaneously. With dout outside the process, dout is updated when s1 changes. There is a delta delay between s1 updating and dout updating, but in terms of hardware this is just a wire.

if I want to use just unsigned arithmatic, can I use std_logic_vector with unsigned library?
thank you
Click to expand...

You can, but std_logic_unsigned is not part of the VHDL standard.
 
TrickyDicky said:
No. s1 is updated to s1+1, and dout is updated to s1 (The old value, not s1+1). Hence it is 1 clock cycle behind s1. This is the rules for signals, as they are not updated until a process suspends. There is no delta delay as they are both updated simultaneously. With dout outside the process, dout is updated when s1 changes. There is a delta delay between s1 updating and dout updating, but in terms of hardware this is just a wire.
Click to expand...

You're right, If I use variable istead of signal, what happen? both of them was same or not?
In professional work variable use or not? for example in below code it use variable or it's not routine?
for assign a variable to out port or signal, what place is better?

Code: 
dout : out std_logic _vector(7 downto 0);
...

process(clk,rst)
variable s1 : std_logic _vector(7 downto 0);

begin
if (condition is true) then
s1 := s1 + '1' ;
? dout <= s1;
end if;
? dout <= s1; 
end process;

another question: When I use synchronous reset in process,I must zero which one? Out port or intermediate signal?sometimes I reset out port and I see XXXXXXXX (unknown vector) in simulation, and sometimes I don't reset out port and I see UUUUUUUU (uninitialized signal) in simulation? What I do ? :cry:
Thank you so much
 

There is never a need to use a variable in synthesisable code - you can do everything with signals. Variables can make the code more readable, but only if you understand what logic is going to be created. There is no difference wheterh you assign a port from a variable or signal - the important thing is the code behaviour and what logic will be created. I would suggest avoiding variables until you know what they will create.

For your second problem, you didnt post the real code, so I cannot say what the problem is. If the code you have posted is like your code, you have assigned dout twice, hence the XXXX.
 

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