Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Scaling down means reducing the sizes of a transistor. Since if the size of a transistor is reduced , the no of transistors in a IC will be more.
Scaling follws the pace with which MOORE has described.
Below are the few process with problem and solution:
Process Problem Solution
180nm Conductors become too resistive Replace alum. with copper
130nm Features smaller than light wavelength Computational lithography*
90nm Limitations on active current Strained silicon
45nm Gate leakage limits scaling Hi-K metal gate
22nm Loss of channel control Tri-gate transistor
There are lot of articles in the internet on the same , you can explore.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
