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How to design AND Gate using one pMOS and one nMOS

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preet said:
apply input A on Drain, B on gate and output Y on source, it will work like And Gate
Click to expand...

Please elaborate. What do you mean by above sentence. Is it nMOS or pMOS or connected together in series or in parallel.

Having an image would be even better.
 

its for NMOS:

A B Y
0 0 0 as transistor is off, Since B is Zero
0 1 0 as transistor is on, Since input A is at 0 thus output is zero
1 0 0 as transistor is off, Since B is Zero
1 1 1 as transistor is on, Since input A is at 1 thus output is 1
 

Ok. This is good.

Just to get a better picture.

When you give B = 0, How can you say the output is 0?
When you give B =1, and A=1, are you sure of getting 1 as output?. Or it is degraded output :).
 

When B=0 then it will be floating but if you add a pulldown load then it will turn to zero
 

preet said:
When B=0 then it will be floating but if you add a pulldown load then it will turn to zero
Click to expand...
And then A and B are all changed to 1, output will be 1? even if it's connected to a pulldown load?
 

Practically, It is not possible to have an AND gate with single MOS. :)
 

Prashanthanilm said:
AND with Diodes:https://en.wikipedia.org/wiki/Diode_logic#AND_logic_gate

So, What is the minimum no of Transistor required to create AND logic?
Transistor:MOSFET'sS

- - - Updated - - -

3 I suppose?.

Coming to the Question raised:

AND gate cannot be created using a Single pMOS and a Single nMOS.
Click to expand...

A fact is In cMOS technology you can only implement all the logics with a bar on the above.......
so you can't get a 0 with 00 in a single stage.
 

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