chipscope signal acquisiton

hello

I am having some problem in understanding signal acquisition from chipscope.

please see the following images. they are 125 MHz clocks and one is 200 MHz clock. What is evident is that clocks are not smooth or synchronized..i.e. the HIGH and LOW time increase and decrease.

Note that the sampling clock is 12 MHz (i guess so, please see the second image and if possible if this clock is in actual the sampling clock?).
I am afradi that this incorrect result has something to do with the 12 MHz clock since it is very very low in contrast to the 125 or 200 MHz clocks.



bests,
Shan

The 12MHz Clock in 2'nd image is not a sampling clock. It's a clock for transferring stored data from FPGA to Analyzer. Stored data are sampled with a internal clock on FPGA.
In FPGA all data will be sampled by the clock that you specified for sampling. from your descriptions I can not understand witch is the sampling clock.(125 Mhz or 200 MHz)

If you used Core Inserter, you connected a net to CLOCK port (and some nets to DATA ports) and that is sampling Clock.

Port Map said:

The 12MHz Clock in 2'nd image is not a sampling clock. It's a clock for transferring stored data from FPGA to Analyzer. Stored data are sampled with a internal clock on FPGA.
In FPGA all data will be sampled by the clock that you specified for sampling. from your descriptions I can not understand witch is the sampling clock.(125 Mhz or 200 MHz)

If you used Core Inserter, you connected a net to CLOCK port (and some nets to DATA ports) and that is sampling Clock.

Click to expand...

thank you for reply... ok now I understand. so the sampling clock is something that I have given inside while I was using core inserter, my sampling clock is 125 MHz.
so how to get data accurately since the 12 MHz clock is to capture data from FPGA buffer to the chipscope pro analyzer. but the thing is it is too slow and the buffer gets full and (I guess refilled afterwards)
(note that I am using repetitive trigger).

One more thing. In the case you said, i.e. the data is stored in buffer inside fpga, then transferred at JTAG clock rate to PC, the clocks shown here (which are the outputs from the clock manager) should be of constant on/off period...why vary?

bests,
Shan

You shouldn't really connect clocks to the data ports. Unless they are a lot slower than the sampling clock (at least half the speed or slower) you will get rubbish (read up on niquist). The transfer clock will be a red herring. The fpga buffers a load of data and then transfers it, it will not affect the data.

usually, you connect the system clock ti the sample clock then data or other bits from the same clock domain. Connecting stiff from another clock domain usually make things look broken

so how to get data accurately since the 12 MHz clock is to capture data from FPGA buffer to the chipscope pro analyzer

Click to expand...

buffers will be filled after trig, and no over writing will be done after it, and they will be freed after reading from Chip Scope.

One more thing. In the case you said, i.e. the data is stored in buffer inside fpga, then transferred at JTAG clock rate to PC,

Click to expand...

note that jtag clock is a clock to transferring data from FPGA to PC, but this transferring is in serial mode(USB is serial)

the clocks shown here (which are the outputs from the clock manager) should be of constant on/off period...why vary?

Click to expand...

this question replied by TrickyDicky.