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What is Link Library In Synopsys Design Compiler..?

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giggs11

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synopsys link library

Hi all,

I have several question regarding Synopsys DC :

(a) What are design references? It was mentioned in the documentation that Link Libraries are needed for design references..

(b) What are Link Libraries. I know target libraries is the one used to bulid a circuit from a translated RTL design. But what are link libraries for...?

(c) I have two separate .DB files/libraries...one for the core cells and another for the IO pad cells. Can I specify two DB files/libraries under Target Library in the setup file. If I can, can you show me the syntax. If can't, should I merge both libraries...?

(d) Whats a Search Path..?

Hope someone can assist me with these queries.

Thanks.

(e)
 

synopsys library compiler

link lib contains model for all cells, pads, custom modules, you must include std lib to link lib, but do not add unnecessary lib to target lib, otherwise dc may use wrong cell.
 

design compiler library

Hi giggs11,

The search path is used to tell DC which directories can be used to resovle the

reference.
 

design compiler link library

Hi, you can see the DC user guide maual.
You can find any questions that you want to know.
 

synopsys dc specify library

hi,
you can see the SOLD of Synopsys.
 

synopsys link library target library

in general , link lib and target lib must be the same.
 

synopsys design compiler link to verilog

giggs11 said:
Hi all,

I have several question regarding Synopsys DC :

(a) What are design references? It was mentioned in the documentation that Link Libraries are needed for design references..

(b) What are Link Libraries. I know target libraries is the one used to bulid a circuit from a translated RTL design. But what are link libraries for...?

(c) I have two separate .DB files/libraries...one for the core cells and another for the IO pad cells. Can I specify two DB files/libraries under Target Library in the setup file. If I can, can you show me the syntax. If can't, should I merge both libraries...?

(d) Whats a Search Path..?

Hope someone can assist me with these queries.

Thanks.

(e)
Click to expand...

Firstly DC construct design using instance name. in linking phase, it find out all modules description that instance related with. For modules that are described by Verilog or VHDL, they are stored in computer memory in GTECH(before compile) or target library( after compile). but macros are provided in .DB format. you need tell dc where can find the macros.
so, link_library consist of *(cpu momery), target_library(generall logics), macros.DB.
Don't need merge standard_cell and io_pad.
set only standard_cell to be target_library,
set standard and io_pad to be link_library. it is ok.
 

compile program link library

module_name U_instance(..);

module_name is a reference,
when module_name is from a lib,
you must link the the lib;
 

synopsys db library macros

your design has standard cell, IO and some macros like memories. IO and macros libraries are used in the link libraries so that the design is synthesised using the target standard cell library. but synthesised macros are used to reference using link libraries.
 
synopsys add .lib files design compiler

It seems link library and target library both are same function. Why bother to use two library ?
 

gtech cells in design compiler

And also .. if you have done your hard macro from other team . and it save as library (*.db) .. you can also including it .
 

synopsys design compiler db

link library for cell instance in the verilog design, target for infer (synthesis) cell for std cell library and the other library. for example, u have a memory called SRAM4k which generated by the memory complier, u have the corresponding library sram4k.db, u should add the sram4k.db to ur link library, it is not neccessary to add it to the target library.
 

synopsys library compiler index

search path are library & working dir
 

compile -incr synopsys

You can download <Advanced.ASIC.Chip.Synthesis> book in EDA E-book upload/download forum.
You can easily find the answer through it.
After you have a general idea obout DC, you can then can refer to SOLD for detail.

Best wishes
 

design compiler library file

if you insert io pad into your rtl code in dc, you need set io pad lib to target lib, otherwise ,you don't need set.
only set standard cell lib to target.
 

u add these lines to ur """ .synopsys_dc.setup"""" file in your project directory

lappend search_path /home/student/lab/ref/db
set synthetic_library {dw_foundation.sldb}
set target_library "sc_max.db"
set link_library "* sc_max.db $synthetic_library"
define_design_lib work -path ./work

the first line indicates the path of the sc_max.db file loaction

note : U please put the correct search path , give the path where ur sc_max.db resides ok then it will solve all the iisues related to link library
 

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