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a question about dft in design compiler

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zzczx

zzczx

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hi members,there is a dft question about the section in the book:
advanced asic chip synthesis,using snopsys design
compiler,physical compiler and prime time.

at the section :8.3.8 Logic Un-Scannable due to Memory Element
the author suggests that shortcircuiting all the inputs feeding
the RAM to the outputs of the RAM, through a mux to avoid the
combinational logic become un-testable .

Does this means that we must add the mux to the netlist manually?
Is there any design compiler command tho perform it?

thanks in advance.
here is the figure:
 

Hello, zzczx.
You need not to add MUX in your design. You can use BIST to contain the Memory in RTL codes and synthesis the design. Then during DFT, you use ""set_scan_element false Path/Memory", the DFT tool automaticlly shortcutting the memory and treat it as a blackbox. This is one kind of method that can solve the testing of memory in design.
 

In our design, we add the multiplexes into RTL code manully to bypass memory in scan mode.
 

We add the MUX at RTL code, control by scan mode.
 

use memory shadow logic inserting in DFT Compiler.
 
add the MUX at RTL code control by test mode which will be '1' during scan testing
 

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