The Borrowing Time in Latch-based design

Question1:
The PrimeTime User's Guide version 2010.6 page 5-2.
it said:
A design using level-sensitive latches allows a combinational logic path with a delay longer than the available cycle time as long as it is compensated by shorter path delays in subsequent latch-to-latch stages. For the two-phase design, the available time for latch-to-latch paths is half the clock cycle.



"allows a combinational logic path with a delay longer than the available cycle time"? I think it's wrong judging from the Figure.

The cycle time is 10ns or 5ns. In 5ns case, it's obvious correct.

The combinational logic path can be longer than the Cycle time(Tclk)?
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Question 2
here is the link about it in STA
http://www.vlsi-expert.com/2011/03/static-timing-analysis-sta-basic-part2.html

It said that this method (latchs. Level-trigger) can reduce the delay of computing time than in Flip-Flop(edge-trigger) case.
The orginal sentences after the example he illustrated in this blog:
"Note: A latch-based design completes the execution of the four logic stages
in 20 ns, whereas an edge-triggered based design needs 32 ns. "

Is it correct? I'm puzzled about it.

Anyone can explain it in detail about the borrowing time?
Thank your very much in advance

echoas!

Question 1:
Yes, you are confusing "cycle time" to be the total high-and-low period of one of the phased clocks.
Cycle time is instead the duration of an active clock pulse, Tclk/2 (time to cycle through each latch stage).

Question 2:
The example shows four stages, and the longest logic delay of *any* stage is 8ns.
Because borrowing does not occur with flops, the period must be at minimum 8ns and the pipelined delay to progress the signal through all four stages is 4*8=32ns.
But with latches, borrowing behavior instead allows a shorter cycle-time of only 5ns (the worst-case of any stage where all of its allowable borrowing is used up), thus 4*5=20ns.
In other words, a latch-based approach would allow you to safely use a clock freq that reduces the overall latency to progress the signal from start to end.
(Note these examples ignore other factors like setup and clock-out delays which would further erode the minimum cycle time and period.)

BTW, do not overlook the fact that latch-based design is more complicated to implement using modern RTL synthesis tools.
That is why it is not commonly encountered for typical synchronous designs.

jrwebsterco said:

Question 1:
Yes, you are confusing "cycle time" to be the total high-and-low period of one of the phased clocks.
Cycle time is instead the duration of an active clock pulse, Tclk/2 (time to cycle through each latch stage).

Question 2:
The example shows four stages, and the longest logic delay of *any* stage is 8ns.
Because borrowing does not occur with flops, the period must be at minimum 8ns and the pipelined delay to progress the signal through all four stages is 4*8=32ns.
But with latches, borrowing behavior instead allows a shorter cycle-time of only 5ns (the worst-case of any stage where all of its allowable borrowing is used up), thus 4*5=20ns.
In other words, a latch-based approach would allow you to safely use a clock freq that reduces the overall latency to progress the signal from start to end.
(Note these examples ignore other factors like setup and clock-out delays which would further erode the minimum cycle time and period.)

BTW, do not overlook the fact that latch-based design is more complicated to implement using modern RTL synthesis tools.
That is why it is not commonly encountered for typical synchronous designs.

Click to expand...

Yeah, The cycle time is the half of Period of time is correct.

In The question2, elimiating the memory elements(latches and Flip-Flops). The minimum computing time is the delay of the whole combinational logic delay. When we use the Flip-Flop. according the synchronous way. The computing time is determined by the time of critical path(8ns). then 4*8=32ns. we can get the correct results.
However, when we can use the borrowing time technique in latches whose cycle time is 5ns. But the whole combinational logic delay must be less than or equal to 20ns(four stages).

Now My mind is clear. If i'm wrong, please let me konw.
jrwebsterco,
Thank you for your reply.

can you give me all the figures in this link, My internet can not completely access it

http://www.vlsi-expert.com/2011/03/static-timing-analysis-sta-basic-part2.html

regards
echoas.

Regarding your comment ...

However, when we can use the borrowing time technique in latches whose cycle time is 5ns. But the whole combinational logic delay must be less than or equal to 20ns(four stages).

Click to expand...

I would not think of it exactly that way.
Instead, you need to consider each of the latch *pairs* involved in the borrowing.
One stage borrows from the next one (only if needed), and the logic delays for both latches in a given pair combine/borrow to determine the minimum cycle-time.
Thus, it is not a function of the "whole combinational logic delay" of all four stages, but instead is the *maximum* time required by the worst of any of the pair-combinations, taken one at a time.
(this is very similar in principle to what you correctly stated about the flop situation)

To work backwards to determine a minimum cycle-time (which I think is what you are really trying to do) ...
You could sum the delays for each pair-combination, and then pick the maximum sum (in this case, it is the path1/path2 combo with 8+2=10ns).
One-half of this is the minimum cycle-time of 5ns - the latches are effectively doing a kind of delay-balancing operation here.

However, note that in general, the duty-cycle of the two phased clocks do not need to be 50%/50%.
(but then things would otherwise get much more complex to explain)

Regarding the diagrams, I would prefer to not copy and post due to possible copyright issues with that site.
Instead, I can also see these diagrams if I do a Google search for "time borrowing blogspot" and then only search for images.
You can see the two diagrams at the top of the search results with the title "vlsi-expert" underneath them.

jrwebsterco said:

Regarding your comment ...


I would not think of it exactly that way.......

Click to expand...

Hi, jrwebsterco,
Exactly, when we use the borrowing time technique, we must analysis the two adjacent latches. No matter in flip-flop or lathes situation. The computing time is determined by the so called worst case(longest path). get it. Thank you for your reply. I really appreciate it.

regards
echoas.