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[SOLVED] Creating Milkyway library with macro .lef file

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dw_man

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I am trying to create a Milkyway library which includes the physical library for a RAM macro. I have the .lef file from the RAM. Can I do this from the Design Vision tool using the create_mw_lib command or will I have to do it from the Milkyway Environment.

I am currently creating the Milkyway library using the create_mw_lib command in the Design Vision tool (using topographical mode) to create the Milkyway library using my reference library.

Thanks
 

You have to create such MW reference libs (FRAM views) either within MilkyWay or within ICC.
SolvNet will show articles if you search for "create FRAM", and there is also a LIBPREP RM-script package available for download as well.
You can also read though the MW docs but it is much easier to copy/paste from a SolvNet article example.
 
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    dw_man

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LEF generally read by cadence tools.
FRAM is the LEF equivalent in Synopsys tools.
 

Thanks,

Yes, I managed to create another MilkyWay reference library using the FRAM view of the .lef file and now the check_library command passes with the logic library being consistent with the physical library.

I have included the .db file in the link library. How do I instantiate this RAM macro in my VHDL? I have tried:

mem1 : cell_name port map (....);

but it is telling me that cell_name is unknown when I try to compile the top level VHDL. Is there something else I need to include in the VHDL such as dont_touch?

Thanks.
 

Do you have a "component cell_name is port (...); end component" declaration anywhere for the macro? (e.g. at the top of your architecture body)
Is an error occurring during elaboration and link, or not until the actual compile command is issued? (are you suppressing any link messages?)
Also double-check that the actual cell name in the LEF and DB is consistent with your VHDL cell_name - perhaps you are instead using the library/file name which might be slightly different (e.g. with a suffix for the characterized P/V/T-corner).
 
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I see, it was at the analyze command that I was having trouble with. But, as you say, I didn't realize I still had to declare the component which seems to have fixed the problem.

My cell_name is the same as in my LEF file and in the LIB file. I converted this LIB file to DB myself. The LIB/DB filenames do have a suffix. I assume this is fine as it is the cell names inside these files which are important?
 

I'm not a fan of VHDL due to heavily-typed requirements like that - Verilog does not have a similar requirement.
But I suspect that VHDL-93 and newer versions might only require this for black-boxes (which is what your RAM macro is, since it is not described in RTL anywhere as an entity/architecture).
But don't quote me on that - I'm that much of a VHDL expert.

Yes, the cell name is what matters inside the RTL code.
Typically there will be at least three libraries for min/typ/max characterized speed corners, with different suffixes to names for the library & filename.
But the cell name obviously must not differ across the multiple libs.
 

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