Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Why not Threshold voltage drop in NMOS switch ?

Status
Not open for further replies.
prcken

prcken

Advanced Member level 1
Advanced Member level 1
Joined
Nov 1, 2006
Messages
419
Helped
41
Reputation
82
Reaction score
38
Trophy points
1,308
Location
Shanghai
Activity points
4,059
Hi, I was simulating a more complex switch circuit to verify my understanding. But I found it's unreasonable at the beginning.
So, I tried to simulate the single NMOS as below, does anybody know why there is no threshold drop? Vthn for this 3.3V NMOS is more than 700mV.
https://obrazki.elektroda.pl/6657784600_1375071251.png

Thanks
 

I added a capacitor load of 1pF and set the initial value to 0 V .
 

You need a DC load. A capacitor is infinite impedance to DC, thus it will charge up close to Vcc due to the subthreshold MOSFET current.
 

yep, subthreshold conduction always exists. But I can't add a resistor, the actual situation is capacitive load.
as the voltage at the source charges up, the VSB also increases, so that VTH increases, too, due to the body effect. the final voltage seems not the VDD-VTH, where the VTH is annotated from the DC operating point.
 

Try this with a resistive load..... and u can see as a resitive network

cap acts as an infinte resistance load...

and another thing is in this configuration Nmos doesnt act as a Pass gate it acts as a diode connected load...

it acts like a ordinary resistance connected to a cap to the DC supply...

And according to my understanding... MOS drops VTh when it is in TRIODE region or In Active region....
otherwise it acts as an open circuit....

Any doubts please let me know it.. All the best..
 
Last edited:

thanks, kennambo. in theory this is well understood, in switched-cap we also simulated with clock, no problems.
I just first time to do transient simulation check with a constant voltage.

yes, it is like a diode connected, it always at saturation region since the gate and drain are connected to VDD, the effective resistance of the NMOS is relatively large since it's at saturation region. there is no DC current path due to its capacitive load, so, in DC sense, the voltage at the cap node will be equal to VDD given infinite time unless the NMOS is completely off.

use resistive load will surely form a resistive divider.
 
So the VTh drop is a factor when we apply Transcient signals to the Drain,,,,

otherwise there is no path for Current and voltage drop... isn't it?

Am i right?
 

it will have an initial voltage stored on the load capacitor, it's zero unless set to other value. And the annotated DC operating points do show some drop, you can build a simple circuit to see if its exactly a VTH drop.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top