[SOLVED] Synopsys IC Compiler vs Custom Designer

what is the difference between Synopsys IC compiler and Synopsys Custom designer ??

Can I use any of them to custom design SRAM cells for example, and use that cell with Design compiler (the same way we use logic gates as predesigned cells) ??

ICC is for P&R of std-cells flow, while Custom Designer is full-custom layout so the latter is more what you want.
(and it is possible that not all versions of it include schematic-entry, and other EDA companies also make decent custom schematic/layout tools)
However, before you can use it through DC, you would still need to formally describe and characterize a RAM macro for timing & load delay effects and so on into the Liberty library format, and finally create a DB-library for use in DC, all of which involves other tools incl. Library Compiler.

I doubt Custom Designer will do those added steps for you - Synopsys unbundles such features across their other tools 'cuz not everyone wants them.
Go to synopsys.com, click under Tools -> All Tools, and you can find the product datasheets for all of their products.

So if library compiler is installed that means I can do it. design a cell, describe it in liberty library format and use it in DC ??

It all depends on how accurate you want it to be, and whether or not you have an example Liberty description of a RAM already available.

Creating Liberty from scratch is rather advanced, and even modifying one by hand is not commonly done except for simple macros that can safely be described using just a few "data points" to describe e.g. the output transition time as a function of loading.
(I am referring to lookup tables - LUTs - being rather simple here, e.g. just needing 2x2 or 3x3 hand-entered data points in the LUT might be enough)
There is a lot of detail that must be correctly formatted and ordered in a Liberty file - a working example to copy from goes a long way towards saving you the trouble of reading and learning through all of the syntactical details.
(but you still need to understand enough to know how to correctly modify the file, kinda like being able to easily modify a VHDL design but struggling to create a VHDL design completely from scratch)

If you already have Liberty (.lib) files to take a look at for your current std-cell library, then you can begin to get a feeling for what they look like.
(and some vendors will not provide you the .lib Liberty source, but only the post-compiled .db)

The comment about accuracy has more to do with needing to involve additional steps well beyond what you've oversimplified.
I am no expert with all of these steps, but here is a basic rundown ...
1) Create a correctly functioning macro (e.g. RAM) design, via the usual schematics and layout and LVS/DRC and so on.
2) Extract the layout, to create an accurate SPICE netlist which includes layout parasitics.
3) Setup and run many iterations of SPICE simulations across different input-pin transition times, output-pin loadings, P/V/T operating-conditions and so on.
(this can involve LOTS of sims and resulting generated data, depending on complexity of function and also on proper strategy to determine and safely bound e.g. setup/hold times for flop-like synchronous inputs w.r.t. a clock and so on)
4) Take the area, pins, function and the generated SPICE data for the macro and format all of it into a Liberty file.
e.g. the generated data must be formatted into LUTs using input-transition and output-load as the indices to a 2-dimensional LUT for each output pin for delay rise & fall and transition rise & fall, or for each type of timing check such as setup rise & fall and hold rise & fall for input pins, and so on (that's four LUTs per pin)
5) Compile the Liberty into a DB using e.g. Library Compiler.
6) In a P&R utility (e.g. Milkyway), identify the legal router pin-hit areas on the layout (e.g. via tagging metal layers with pin names and so on).
Likewise identify which metal layers are legal for a P&R router to route over the macro, if any (this relates to parasitic/coupling effects that might be harmful to accuracy of operation).
Then create a cell abstract of the macro layout (aka FRAM view) and update/link it with the DB from above (if you are also doing timing-driven P&R).

You would now have a macro which can be used in DC (using the DB) and subsequently in the P&R tool (using the Milkyway FRAM view).
(the same steps would generally apply to each std-cell in a library)
Note there are other more subtle details that I have omitted, such as a need for output delays to be increasingly monotonic as a function of loading (otherwise synthesis tools can give poor QoR when they try to resize cells during optimization to mitigate with excessive delay and transition times).

Keep in mind that Synopsys and others make tools which will automate steps (3) & (4) above, but a human still must first create setup files and templates.
(look for Synopsys' Liberty NCX or their newer replacement which I believe is SiliconSmart)
Also, I am not an expert with the P&R tool steps, so something is probably wrong or missing.
But at least this should give you an idea of how things are done if accuracy and completeness are important.
I am also not personally familiar with a comprehensive text or app-note that covers all of this, but there might be one if you searched for the right words.

Thanks a lot.