VCS mixed mode compilation - no optimization

Hi,

I am doing some mixed-mode (VHDL + Verilog) simulation. My testbench is in VHDL and the I have two other modules which are written in verilog in two separate files. I have also generated separate SDF files for each of them. I followed the following procedure to run the testbench:

1) compile each Verilog file
vlogan <verilog files>

2) compile vhdl testbench
vhdlan <testbench>

3) run vcs and pass the name of SDF file to them.

But there are some warning when adding the SDF file that means it can not find some instantiation in the design. I've noticed that the VCS optimize some modules which seems are unused or doesn't do anything and remove them from the design. I could open the new Verilog in the DVE and see that some modules are removed. What I want to know is that how I can tell VSC to not to do any optimization?

Thanks

You could try the -O0 or the -debug_all option (or both) to "vcs" executable - turns off many optimizations.
But, I've also never seen VCS complain about SDF annotation being affected by optimizations you mention (but not Radiant Technology option cannot be enabled for SDF, but you also did not indicate enabling that).
BTW, SDF should only refer to leaf-cell (i.e. std-cell or hard-macro) pins and instances, and not hierarchical modules.
(it does *use* the hierarchy to reach down to these leaf-cells, but does not refer to pins on hierarchical modules)
That is why unused ports or modules (e.g. that do not reach or contain any leaf-cells) should not cause such problems.

Maybe some leaf-cells disappeared between when SDF was generated and the final netlist(s) was written out?
Maybe you are forgetting a link-library? (but I'd think you'd then see other messages about that)
Maybe you should include an example of an SDF-annotator message?
Or at least chase down the line in the SDF file it refers to and see if there is a hint to follow? (including going back into the tool that generated the SDF to gain more info on what cell it relates to)
This is all somewhat obvious flow-debug stuff.

I also recall issues with VHDL modules/entities having complex-type ports (e.g. structures or multidimensional arrays) being instantiated inside of Verilog, but I am expecting that this issue went away once SystemVerilog was supported (which now also supports such things).

Amir Yazdanbakhsh said:

Hi,

I am doing some mixed-mode (VHDL + Verilog) simulation. My testbench is in VHDL and the I have two other modules which are written in verilog in two separate files. I have also generated separate SDF files for each of them. I followed the following procedure to run the testbench:

1) compile each Verilog file
vlogan <verilog files>

2) compile vhdl testbench
vhdlan <testbench>

3) run vcs and pass the name of SDF file to them.

But there are some warning when adding the SDF file that means it can not find some instantiation in the design. I've noticed that the VCS optimize some modules which seems are unused or doesn't do anything and remove them from the design. I could open the new Verilog in the DVE and see that some modules are removed. What I want to know is that how I can tell VSC to not to do any optimization?

Thanks

Click to expand...

Hi,
Can you help me with the 3rd step of the process that you mentioned. I have VHDL design and testbench, and I don't know how to tell the compiler the name of the SDF file.

Thanks

Chapter 10 of the User Guide titled Gate-level Simulation should adequately explain the usage of the -sdf elaboration command-line option for you.