FPGA implementation of FPGA decoder

FPGA implementation of LDPC decoder using VHDL

I am implementing LDPC decoder with the use of belief propagation in log domain and platform is VHDL.but in LDPC there are so many exhaustive formulas including matrix calculation,tanh functions and some small small formulas as well.I am not getting how to implement those formulas in VHDL.

How far have you got?

hi sougata
i face those problems before
when i try to implement sum product i think about making it with LUT(look up tables ) for the tanh and tanh-1 but we found it will take alot of resourse of our FPGA so we use approximate sum product the different between them is only 0.2 dB as i remeber so i think it is not a big different in bit error rate.
this is the approximate sum product equations where where it is easy to implement epsi using a lookup table because it maximum value is 3 and min is 0.
if you need any help feel free to ask .

Till now manually i have calculated the whole algorithm in pen-paper using BP in log domain for LDPC decoding.The output is coming for regular LDPC only but i have some doubt over irregular LDPC.so i started the coding considering the regular LDPC only.but my doubt to overcome those floating point and tanh calc is cordic needed? how to implement the formula for AWGN which is 4y(i)*Es/N0?and last doubt how to implement the parity check matrix....is only building up a array is sufficient...plz help me in clearing those doubts....i am attaching the block diagram which i am implementing..please also tell me am in correct path?

hi sougata
1) the design i have used before can be applied for regular LDPC and also can be applied for irregular column LDPC .
2) as i remeber the any algorithm of BP can be applied for regular and irregular LDPC .
3) we didnt use cordic to over come the floating point and tanh calculation we have make our floating point representation according to the BER we decide and give it to the Demapper .
ex we say if the i/p LLR is 0.03125 so in verilog it is represnted as 0000001
LLR is 0.06250 so in verilog it is represnted as 0000010
LLR is 0.09375 so in verilog it is represnted as 0000011
so if we add 0.03125 + 0.06250 =0.09375
in verilog 0000001 +0000010=0000011

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4) 4y(i)*Es/N0? as we need this to test our system so we made it by matlab (at start we generate a random binary bits an put it in the test bench of encode an then write it on a txt file and read it from matlab then add additive white gaussian noise then we write it in the testbench of Decoder then write the o/p decoded bits in a text file and then compare using matlab with the generated random binary bits then we repeat this for diff. SNR and then we draw SNR with BER.

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5) about the paritycheck module we decide not to make it as the system we made for is using a very very big LDPC ex.(23400,64800) matrix so we thougth it will make avery large delay to our system to find the syndrome so we decide to have the maximum number of iteration of 10 then after 10 itteration we get the o/p.
but i wish if your system is usig a small Ldpc codes so if you can make it ,it will save alot of processing time .

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i want to know will you design it fully serial or fully parallel or partially parallel.

I am implementing it for parallel structure but plz let me know is it possible to implement the full LDPC decoder in VHDL...means without using MATLAB

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bcoz i didnt use MATLAB before