beeflobill
Member level 3
I'm trying to debug a bus contention issue in Verilog. My problem is that I'm having trouble identifying which drivers are contending on the bus. Is there a way to list all the drivers to a wire and what they are attempting to drive? Or, is there a better method for doing this?
By the way, I'm using nc-verilog, but if you have a solution in a different tool I'd still be interested to know because any inputs or concepts would be helpful.
I found a similar question at https://www.edaboard.com/threads/281838/
Thank you.
By the way, I'm using nc-verilog, but if you have a solution in a different tool I'd still be interested to know because any inputs or concepts would be helpful.
I found a similar question at https://www.edaboard.com/threads/281838/
Thank you.
