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bug!! port connection problem verilog modelsim

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It is a simple port connection, as seen in the first figure, there is no problem with the port B_mem. But if go to A_mem prot, a error occur, which is "VSIM-3096, imcompatiable with "........" unpack can not assign to pack".
Then I split it like shown in the figure. but when pass the value "H_mem_0" to "A_mem_0". the A_mem_0 becomes high impedance. but the value of "H_mem_0" does not have any problem.
 

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The error message is giving you a hint. Somewhere in your code, which we can't see, you have tried to connect an unpacked array to a packed one, which you cannot directly do. For example:

If you have declared the output of one module to be:

Code: 
output  logic    A_data[15:0];   //This is an unpacked array

And you have declared the input of the second module to be:

Code: 
input logic     [15:0]  B_data;  // This is a packed array

Then at the top level you could not directly connect the two ports and the simulator would complain of a packed/unpacked connection issue such as you are seeing.

Double check your memory modules to ensure that this is not happening.

r.b.
 
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