Do I need to set input and output delays in design compiler?

Dear all,

I have a question about setting input and output delays in RTL compiler.

I know the definition of input and output delays and why it is necessary to set them in order to be able to interface with external devices.

However my question is this:

I know that in my front-end the external device launches the data on the falling edge of the input clock and my system will capture it in the next rising edge of the input clock. Also on the back-end I will launch the output data on the falling edge of the output clock and my external device will capture it on the rising edge of the next coming output clock. And my clock period is 1600ns (625 KHz). So i have ~800ns time for data to be stabilized before capturing it at the input and output.

So, knowing this, is it still necessary for me to set input and output delays in RTL compiler? Because I think there is no chance to miss a data at the input and output ports. Please correct me if I am wrong!

Thank you so much for your attention.

Looks like you have half clock period setup time instead of full clock period. Clock is slow so timing closure may not be a problem. But, its always better to constrain the path by mentioning input and output delays. If you don't constrain, the tool will not report any violation if any exist in that path.

Thanks Morris for your reply.

Yes, exactly. I have half a cycle set-up time

As far as I understood by reading the Encounter RTL compiler user manuals, setting the input delay is critical when we need to capture the data at the input at same clock edge which it was launched, so extra delay is introduced by the design compiler by adding extra buffers in the data path so that the data is captured at the next clock edge in the input. So why should I add extra hardware to my design while I know that I'm not gonna get data at the same clock edge as it was launched? So do you think I will be fine if I go without setting input and output delay?

Thanks again

Setting input delay does not mean the " extra delay is introduced by the design compiler by adding extra buffers in the data path". It is accounting for the delay external to your block that needs to be accounted while evaluating your data path delay.

No you don't have to do it. You should just define period. To begin with, don't use set input and set output delay. They can cause unnecessary confusion and debugging.

Later on, you can use these.