sidir
Newbie level 5
I am using Altera Nios and has question about Avalon bus slave fundmental transfer. In Avalon bus specification, slave fundmental read transfers data from peripheral to bus module immediately after "chipselect" and "read" signals are asserted. Does this mean the read transfer need no "clk" signal? I plan to design the peripheral as: seeing "chipselect" and "read" both = '1', then output "readdata", otherwise register the value of "readdata". No synchronization to "clk". Will it be correct? Thanks!