onion2014
Member level 1
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module which_clock (x,y,q,d);
input x,y,d;
output q;
reg q;
always @ (posedge x or posedge y)
if (x)
q <= 1'b0;
else
q <= d;
endmodule
In this, how does the synthesis tool, figure out which is clock and which is reset. Is the statements within the always block is necessary to find out this or not ?
I think the answer is yes. the synthesis tool should have templets to figure out which one is rest which one is clk. otherwise, it might connect the clk to the rst pin of the fflop.
plz share your idea.
input x,y,d;
output q;
reg q;
always @ (posedge x or posedge y)
if (x)
q <= 1'b0;
else
q <= d;
endmodule
In this, how does the synthesis tool, figure out which is clock and which is reset. Is the statements within the always block is necessary to find out this or not ?
I think the answer is yes. the synthesis tool should have templets to figure out which one is rest which one is clk. otherwise, it might connect the clk to the rst pin of the fflop.
plz share your idea.