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how to do the low voltage gate simualtion

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poiu_elab

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we've got 1.8v standcell simulation and layout model(only the digital part).
but we want to use these cell in 1.0v voltage.
we believe that under these environment, the logic of cell is ok.
but the timing is critical aspect of the project design.
so how can we get the gate simulation(post-simulation) result?
 

Gate simulation means two inputs:
1- netlist for functionality
2- SDF for timing annotation, which is generated by prime time for example, for each corners you need, based Alan the liberty/db and the netlist.
Then you load the netlist with this SDF to simulate.
 

yes, thank you for replying firstly.
we know the standard flow of gate simulation
but notice what I mention is low voltage.
we get the 1.8v standard cell library and we can do the 1.8v gate simulation.
but we want to use the 1.8v standard cell under 1.0v voltage.
so the netlist is the same .
but how can we do the 1.0v post-simaltion, as you know, that timing is different from the 1.8v?
 

HI~!

I think the key for what "rca" said is that:
-> you must load the different sdf which generated under 1.0 volt instead 1.8 volt

As we have known, the timing in gate-level simulation is annotated by .sdf
That means no matter how you change the operating condition in simulation, the timing is fixed if the .sdf is the same.


Therefore, the question will be converted to:
-> How do we change voltage for operating condition during PrimeTime ?

But in fact, I never do this before, I can't give you answer about this.
If there is anyone who is willing to share how to do, I'll appreciate this.
Thanks.

Best Regards,
PoLo
 
Hi,

you will need a library which is characterized for 1.0V
with this library you can do your synthesis and your sdf simulations.

Depending on your position regarding the foudary you may get this library or not.
Or maybe your foundary does have a tool for derating an existing library.
Maybe you already have some slow/worst case libraries which fit your request.

Best regards
 
thanks for replying.
I think that your answer is a useful way to realize what we need.
we've got 1.8v library, so if we need 1.0v timing. we will need 1.0v library.
two ways you mention to get this library.
one is ask for foundry and the other one is to get the timing shift different voltage tools to get this done.
is that right?

qieda said:
Hi,

you will need a library which is characterized for 1.0V
with this library you can do your synthesis and your sdf simulations.

Depending on your position regarding the foudary you may get this library or not.
Or maybe your foundary does have a tool for derating an existing library.
Maybe you already have some slow/worst case libraries which fit your request.

Best regards
Click to expand...
 

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