MB1504 PLL locking problems with noise in demodulated output

The MB1504 PLL tries to lock but there is a lot of noise in the demodulated output. What could be the reason? The loop filter calculations seems to be fine.

mb1504 pic

Did you check the noise at the input of VCO
When you say noise, what do you mean?
Is it a white noise noise or some signals?

mc3362 pll pic

The noise means the glitches in the demodulated output PPM signal.

demodulated output

>The MB1504 PLL tries to lock but there is a lot of noise in the demodulated output. What could be the reason? The loop filter calculations seems to be fine.

Check the power to VCO by FFT of Oscilloscope to see if there are low-freq noise.

And check the surrounding of Loop filter in layout to see if possible there are digital noise coupled to the loop filter.

Or VCO gain is too high.

mc145170-2

If it's not the surrounding of Loop filter and layout, Did you simulate the PLL? (For phase a Gain margin) It might be on the edge of stability. You can use Pspice for simulation.

mc145170 layout

The power to PLL is from MAX883, regulated 4V. It doesn't seem to be digital coupling noise either. VCO gain is set to almost 1.15 MHz/V and the receiver is operating at 72MHz and I think at this frequency the layout is not that critical. Have a look at the attached schematic.

How can I simulate PLL using Pspice. Does pspice have MB1504 model?

mb1504 mc3362

In order to lessen the possibility for the loop filter to lower the phase magin and oscillate do the following: 1) increase C26 to 39n; 2) lower C24 and C27 to 39p.
This will move the R18+C26 Zero to a lower frequency and will move the poles of R18+R20+C24+C27 to a higher frequency, so you will have a higher frequency range of the PLL control loop at a 6dB/Octave slope, which has a stable loop phase margin of 90 degrees. Try it and give a feedback to the forum.

demodulated ppm signal

I have changed the value but it doesn't make any difference. I have observed the PLL charge pump output (input to VCO) and its not pure DC even if the PLL is locked (Lock detect pin High). There is a ripple (short impulses) and that is why there is a random shift of output PPM pulses.

Now from where this noise is being introduced. The loop filter calculations seems to be correct... please see the attached doc file. I admit that the layout is not very good but it shouldn't make much difference at 72MHz. Could it be PIC clock or some other digital noise? I have even added bypass capacitors of 100nF at both Vcc inputs of PLL and PIC but doesn’t make any difference.

I have recalculated the filter values by changing fa (the frequency of the carrier, within the desired time ts, after a step or hop) = 100Hz and ts (the desired time for the carrier to step to a new frequency) = 1msec to reduce the loop BW but doesn't make any change. I have used the PLLBasics.pdf document from fujitsu website to calculate the loop filter element values. Vcc is smooth but at very higher Volt/div scale of oscilloscope there is very slight noise and I don't think it is contributing anything the main problem.

pic mb1504

R20 and C27 should be located right next to Pin 23 of the 3362. If they are located by the pll and if the trace is long, it is now a very sensitive high impedance trace and that can cause trouble. Also make sure the ground return for your integrator cap in the PLL is routed right back to the pll.

pll for 20khz to 800khz

If I replace the routes of track from PLL output to VCO input and VCO output to PLL fin by a small coaxial cables with external shield connected to ground, will it work?

And also shifing the coupling capacitors for VCO output and 10.245 MHz Fref for PLL close to MC3362.

pll locking issues

After reading your DOC attachment I have these remarks:
Your loop bandwidth is way too large compared to the PLL phase detector's reference frequency. The loop bandwidth should be at least 10 times lower than the reference frequency, preferably 20 times. However if you lower the loop bandwidth, the settling time will suffer but you have no choice.
When the loop bandwidth is in the same magnitude as the reference frequency, the nature of the operation of the phase detector is like a sampled system and the approximations to an analog linear system breaks down, so the formulas you used to calculate the loop filter components are no good.
Just for checking, compute again the loop components for a loop bandwidth of 1KHz and check if it is working better.
By the way the components values should not be very accurate, just take the closest standard value.

mb1504 control

Thanks strabush for your valuable suggestions.

I have recalculated the loop filter R and C values using the following specs.

Frequency range: 61.310 to 62.290 MHz
Channel spacing: 20 kHz
Maximum frequency change during a step (fstep): 800 kHz
The desired time for the carrier to step to a new frequency (ts): 10msec
The frequency of the carrier, within the desired time ts, after a step (fa): 1 kHz
Damping factor: 0.707
VCO sensitivity (calculated, not measured) (Kvco): 1.126 MHz/V
Charge Pump Current (Icp): 3mA

With these specifications and using the formulae given in fujitsu loop filter calculation document the value of R and C comes out to be:

C24 = 114nF (value used: 100nF)
R18 = 1.2k
C26 = 1.14uF (value used: 1uF tantalum)
C27 = 114nF (value used: 100nF)
R20 = 1.2k

Loop Bandwidth = 517 Hz

Now the output of PLL (input to VCO) is smooth and the receiver has tuned by adjusting L3 but the tuning is highly unstable. There are two problems: First with moving the transmitter away from the receiver the output becomes distorted and it seems that VCO is not tuning. The PPM output is fine by placing the transmitter next to the receiver. Secondly changing the channels by rotary dip switch, the output doesn't change with same transmitter channel (72.190MHz). It is desired that with RX channel change there should be no output until the TX is also changed to the same channel. I have checked the PIC16F84 output (data, clock, LE and LD) and its working perfectly fine by changing dip switch position, since it is in the plugable module form.

Could it be possible that VCO sensitivity is not properly adjusted or changing the values of C14 (68pF) can improve the tuning? L3 inductance is 150nH. Any suggestions...

pll loop filter bandwidth fujitsu

First check the VCO: disconnect the line at pin 22 of IC1, connect a trimmer of a few KOhms from +5V to ground with center whiper to pin 22 of IC1 and check the frequency of the vco with a frequency counter. Make a weak coupling of the counter to the vco (a few turns of wire connected to the counter and held close to L3) to make sure the counter does not changes much the vco range.
After making sure the VCO has the right frequency range (at various VCO control voltages) reconnect the pll loop filter to pin 22 of IC1 and check again the VCO frequency. It should be locked to the wanted PLL frequecy, and should be stable even when you put your finger close to the resonant circuit of the VCO. Make sure the resonant circuit of the VCO (L3, C14) are very close to IC1 with short connections, and that L3 is shielded (not necessary but highly recommended). Check with the frequency counter if the frequency of the PLL is the right one when changing channels with the rotary switches.

pll with mc3362

I am fed up and going to replace the PLL with MC145170-2 and going to redesign the PCB.

Any suggestions for the PCB layout design.

800khz pll with pic

maybe i have the same problem.
i add two bypass cap at the Vt of VCO . 10uf and 100nf
pll works well .
but i don't know why ?
anybody could tell me ?
thanks

mc3362 mhz

maybe i have the same problem.
i add two bypass cap at the Vt of VCO . 10uf and 100nf
pll works well .
but i don't know why ?
anybody could tell me ?
thanks

transmiter mc145170

10.245MHz from the buffered output from MC3362 will drive the reference oscillator input of the MC145170 PLL. Now this PLL has a buffered output REF_out of reference frequency or externally provided reference source to drive something else and can be programmed to have division.

Now my question is that is this a nice idea to drive the clock input of PIC16F84 from this output or should I use an RC oscillator for the PIC?

rx rc mc3362

This mb1504 pll for software send me?

**broken link removed**



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