Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Challenges of DFT and their Explanation

Status
Not open for further replies.
A

amitk3553

Advanced Member level 4
Full Member level 1
Joined
Jul 20, 2012
Messages
117
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Location
DELHI, INDIA
Activity points
1,982
Hell all,

Please tell me about the Challenges in DFT(Design for testability).


Thanks!!!!!
 

Challenges are :
-> To make design fully testable with high number of fault coverage for transition.path delay and stuck-at testing...
 
maulin sheth said:
Challenges are :
-> To make design fully testable with high number of fault coverage for transition.path delay and stuck-at testing...
Click to expand...

Please more elaborate the challenges with path delay and stuck at testing????
 

We just need to increase the fault coverage in any how, with considering the DFT area and power overhead. whether it is through stuck at testing or transition or path delay..whatever it is..
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top