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Zero width glitch in VCD file

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ebrahimi.khoy

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I am doing some functional post-synthesis simulation on Modelsim and I can see lots of zero width glitches in the VCD file. Considering that it is a functional simulation, it seems to be odd.
Any idea?
 

There might be some specify blocks present in the library cells.
 

Have you got any clue? I am also confused with this problem. I am using a VCD file generated by RTL simulation. And using Synopsys 'vcd2saif' command to generate saif file, in which I found a target wire has toggle counts at about 1188. I also write a perl script to count the toggle. It found more than 2700 toggles. Then I searched the VCD file and found that the target wire toggles twice at one time point sometimes.
 

I was using Nangate standard cell library and there was a problem in this library. In fact there was some sort of feedback in some cells and modelsim does lots of iterations on these loops. I removed them and problem solved. Are u using Nangate for synthesis?
 

ebrahimi.khoy said:
I was using Nangate standard cell library and there was a problem in this library. In fact there was some sort of feedback in some cells and modelsim does lots of iterations on these loops. I removed them and problem solved. Are u using Nangate for synthesis?
Click to expand...

can you tell where did you get the nandgate library? Please share the link if it is free.

Thanks
 

tariq786 said:
can you tell where did you get the nandgate library? Please share the link if it is free.

Thanks
Click to expand...


You should register at here
**broken link removed**
After registration, you can download it for free.
 
Thanks for your reply. My VCD file was generated from RTL simulation by Modelsim, no technology library involved.
 

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