pd_789
Newbie level 4
Why do we need to do clock modelling (add uncertainity, latency, transition) though we overconstrain our design with 30% of clock?
Suppose if my design is designed for 100MHz i am applying 130MHz and synthesizing it(and it is passing) still why do i need to do clock modelling ?
Suppose if my design is designed for 100MHz i am applying 130MHz and synthesizing it(and it is passing) still why do i need to do clock modelling ?