Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

LEC conformal problem

Status
Not open for further replies.
V

vikas.m0502

Junior Member level 1
Junior Member level 1
Joined
May 11, 2012
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,389
I am getting "EXTRA" in PI and PO while doing LEC with Conformal.
Do anyone have idea how to resolve this issue ?

I have already used "set mapping method -unreach".
This helped in reduction of EXTRA and UNreachable of DFF's but no change in EXTRA of PI and PO.

Do I have to map these manually ?

Please help.

Thanks.
Vikas
 

That will depend on what type of inputs/outputs these extra PI/PO are.
Are these scanin/scanout? Have you used scan constraints?
Do you really need to compare them?

Why do you want to reduce extra and unreachable DFFs? Since they do not contribute to design functionality, its better leave them unmapped and not to compare them.

Thanks,
-Sandeep
 

There is no scanin and scanout pins. I have already used the scan constraints.

How to decide whether we need to compare them or not ?

Actually these are in large numbers like:
-Out of 166 PI's only 35 are mapped and 131 are Extra.
-Out of 358 PO's only 20 are mapped and 338 are Extra.
Doesn't such large number in EXTRA contribute to something? Or we can just ignore them.

Thanks,
Vikas
 

Are there any name changes in the design causing them not to map? If yes, you will need renaming rules.
 
yes, thats the problem.
Thanks a lot.

- - - Updated - - -

yes, thats the problem.
Thanks a lot.

- - - Updated - - -

Hi sandeep,

Do you know how to match the case in renaming rule.
I need to map "i[ib_cal_done]" to "i_IB_CAL_DONE_I" (and many more of similar pattern).

Thanks,
Vikas
 

As you have applied scan constraints and scan ports are not present in design Synthesis tool has added those PI scan Input and PO scan ouputs.
You can ignore them
 
Conformal command reference has a nice explanation of renaming rules.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top