syedshan
Advanced Member level 1
![Advanced Member level 1](/styles/images/ranks/glevel1.gif)
- Joined
- Feb 27, 2012
- Messages
- 463
- Helped
- 27
- Reputation
- 54
- Reaction score
- 26
- Trophy points
- 1,308
- Location
- Jeonju, South Korea
- Activity points
- 5,134
Dear all,
This is kind of urgent but in no way at all DOING-HOME-WORK-BY-SOMEONE-ELSE kind of thing. I am just stuck with time and have less experience of simulation over VHDL
I usually use verilog for my simulation but this time I have to use VHDL (dont ask why...obsessed with timing
)
Any how the thing is I have to read the entire file as we use to do in verilog with readmemh command and then save respective data to FIFO (for simulation).
I know this might be simple thing but now if someone has a code snippet or web-link please share.
Waitng
bests,
This is kind of urgent but in no way at all DOING-HOME-WORK-BY-SOMEONE-ELSE kind of thing. I am just stuck with time and have less experience of simulation over VHDL
I usually use verilog for my simulation but this time I have to use VHDL (dont ask why...obsessed with timing
Any how the thing is I have to read the entire file as we use to do in verilog with readmemh command and then save respective data to FIFO (for simulation).
I know this might be simple thing but now if someone has a code snippet or web-link please share.
Waitng
bests,