Fish4Fun
Junior Member level 1
FPGA Clock Generation
I am working on an FPGA based DSO project. I would like some input on the FPGA/ADC clock. The project utilizes 2 ADCs capable of up to 250MSPS (Maxim 1121s) and I plan on using a Xilinx Spartan FPGA. For acquisition there needs to be several timebases. These include: 10Mhz, 25Mhz, 50Mhz, 100Mhz, 125Mhz, 150Mhz, 175Mhz & 200Mhz. In addition, the clocks beginning with 100Mhz need a complementary output for interleaving the two ADCs.
I have considered solutions like the ICS511 and the MC12429, but was curious if it would be worth considering a PLL synthesis within the FPGA, or if anyone had any suggestions for a PLL frequency synthesizer chip other than the two mentioned.
Thanks in advance for any input.
I am working on an FPGA based DSO project. I would like some input on the FPGA/ADC clock. The project utilizes 2 ADCs capable of up to 250MSPS (Maxim 1121s) and I plan on using a Xilinx Spartan FPGA. For acquisition there needs to be several timebases. These include: 10Mhz, 25Mhz, 50Mhz, 100Mhz, 125Mhz, 150Mhz, 175Mhz & 200Mhz. In addition, the clocks beginning with 100Mhz need a complementary output for interleaving the two ADCs.
I have considered solutions like the ICS511 and the MC12429, but was curious if it would be worth considering a PLL synthesis within the FPGA, or if anyone had any suggestions for a PLL frequency synthesizer chip other than the two mentioned.
Thanks in advance for any input.