ABO_ATHAB
Junior Member level 1
hi
i try to build Differential Manchester(https://en.wikipedia.org/wiki/Differential_Manchester_encoding) by use vhdl
this is my code but is not synthesizable:-?
i need to be synthesizable
best regards
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.all;
entity main is
Port (
clk,d : in STD_LOGIC;
dm : OUT std_logic );
end main;
architecture Behavioral of main is
signal temp,clkin:std_logic:='0';
begin
clkin<=not(clk);
process(clk)
begin
if(rising_edge(clk)) then
if(d='0') then
temp<=not(temp);
end if;
elsif(rising_edge(clkin)) then
temp<=not(temp);
end if;
end process;
dm<=temp;
end Behavioral;
i try to build Differential Manchester(https://en.wikipedia.org/wiki/Differential_Manchester_encoding) by use vhdl
this is my code but is not synthesizable:-?
i need to be synthesizable
best regards
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.all;
entity main is
Port (
clk,d : in STD_LOGIC;
dm : OUT std_logic );
end main;
architecture Behavioral of main is
signal temp,clkin:std_logic:='0';
begin
clkin<=not(clk);
process(clk)
begin
if(rising_edge(clk)) then
if(d='0') then
temp<=not(temp);
end if;
elsif(rising_edge(clkin)) then
temp<=not(temp);
end if;
end process;
dm<=temp;
end Behavioral;
