need help to fix the error in this verilog code

module code1(A,B,CLK);
input CLK;
input A;
output B;
reg B;
always @(posedge CLK)
begin
B<=A;
end
always@(negedge CLK)
begin
B<=~A;
end
endmodule

Use different registers for different processes. You can use MUX to propagate one of the registers to output.

What is the problem with above code?

Hello all,
Can I know, what is the error in this verilog code?

Prashanthanilm said:

What is the problem with above code?

Click to expand...

Error:different drivers connected to A

The register B could be driven by two different process.

- - - Updated - - -

Sorry the register B could not be driven by two different process.

rca said:

The register B could be driven by two different process.

- - - Updated - - -

Sorry the register B could not be driven by two different process.

Click to expand...

my actual code is

module disp1(A,P,Q,K,CLK,bclock);
input [3:0]P;
input [3:0]Q;
output [3:0]K;
input CLK;
output [6:0]A;
reg [6:0]A;
reg [3:0]K;
output bclock;
reg bclock;
integer count=0;

always @(posedge bclock)
begin
K<=4'b1110;
case(P)
0:A<=7'b0000001;
1:A<=7'b1001111;
2:A<=7'b0010010;
3:A<=7'b0000110;
4:A<=7'b1001100;
5:A<=7'b0100100;
6:A<=7'b0100000;
7:A<=7'b0001111;
8:A<=7'b0000000;
9:A<=7'b0001100;
endcase
end
always @(negedge bclock)
begin
K<=4'b1101;
case(Q)
0:A<=7'b0000001;
1:A<=7'b1001111;
2:A<=7'b0010010;
3:A<=7'b0000110;
4:A<=7'b1001100;
5:A<=7'b0100100;
6:A<=7'b0100000;
7:A<=7'b0001111;
8:A<=7'b0000000;
9:A<=7'b0001100;
endcase
end
always @(posedge CLK)
if (count < 42666) count = count+1;
else
begin
bclock <= !bclock;
count=0;
end
endmodule

/* this code is giving bunch of errors like
Multi-source in Unit <disp1> on signal <A<6>>; this signal is connected to multiple drivers.

anyone please help me to fix

Same idea any signal or register could be assign only bye one process, or in Verilog one assign module.

rca said:

Same idea any signal or register could be assign only bye one process, or in Verilog one assign module.

Click to expand...

I diidnt get you. Sorry. Please do elaborate.

The register B is assign in two different process, and this is not allowed.

Since B is used here on two different procedures, there is an error . Now how to correct this program.
The idea is when posedge B=A; when negedge B=~A. Here however we are summing into one variable B, so is there any way to execute . Just Curious

No physically possible to have a flop stimulated on both edge.
You could create a pure combinational logic
B <= CLK ? A : ~A;
But in this case B is only a wire.
You a clock at double speed to do that.